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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-04-10 14:35:59 -0500
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-04-17 04:41:49 +0200
commit2dbd08faf4be1f2a156730f8857b4c6bb72909e3 (patch)
treead2c5834a0a3a97317eaf5ea0f5682f077d34fe7 /src/southbridge/amd/agesa/hudson/Makefile.inc
parent065b7da298953feaec3563bf753f45cf00fba2c0 (diff)
downloadcoreboot-2dbd08faf4be1f2a156730f8857b4c6bb72909e3.tar.xz
southbridge/amd/agesa/hudson: Add initial support for SMM
This sets up the infrastructure to handle SMIs generated by the Hudson southbridge. An API for interfacing to mainboard handlers is not defined at this point. A few functions are defined to allow mainboard code to enable SMIs from GEVENT pins. These are the only functions which I expect to be needed anytime in the foreseeable future. SMIs are always acknowledged and cleared, as not clearing an SMI will cause us to re-enter the SMI, effectively bricking the machine if a southbridge-generated SMI without a handler occurs. Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5494 Reviewed-by: Aaron Durbin <adurbin@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/Makefile.inc')
-rw-r--r--src/southbridge/amd/agesa/hudson/Makefile.inc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 54a93d23f8..b92e850664 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -22,6 +22,9 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c
romstage-y += imc.c
ramstage-y += imc.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
+
# ROMSIG At ROMBASE + 0x20000:
# +-----------+---------------+----------------+------------+
# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |