diff options
author | Mike Loptien <mike.loptien@se-eng.com> | 2013-07-17 15:14:59 -0600 |
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committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2013-08-15 18:40:11 +0200 |
commit | ac90d8013a26d99df21cb555bb313506ce32979c (patch) | |
tree | 3d5eedc01f54116d49a9aa649d081020d73c8097 /src/southbridge/amd/agesa/hudson/acpi/fch.asl | |
parent | 81c70fb142326fe9e5ac5391cdd45f93c984e3e6 (diff) | |
download | coreboot-ac90d8013a26d99df21cb555bb313506ce32979c.tar.xz |
AMD Kabini: Split DSDT into common sections
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.
Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/acpi/fch.asl')
-rwxr-xr-x | src/southbridge/amd/agesa/hudson/acpi/fch.asl | 118 |
1 files changed, 52 insertions, 66 deletions
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 573fa9ba5b..4fbf853038 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -23,67 +23,54 @@ /* Describe the Southbridge devices */ -/* PCI slot 1, 2, 3 */ -Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } -} - -Device(SBUS) { - Name(_ADR, 0x00140000) -} /* end SBUS */ - -/* Primary (and only) IDE channel */ -Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" -} /* end IDEC */ - +/* 0:11.0 - SATA */ Device(STCR) { Name(_ADR, 0x00110000) #include "acpi/sata.asl" } /* end STCR */ +/* 0:14.0 - SMBUS */ +Device(SBUS) { + Name(_ADR, 0x00140000) +} /* end SBUS */ + #include "usb.asl" +/* 0:14.2 - HD Audio */ #include "audio.asl" +/* 0:14.3 - LPC */ #include "lpc.asl" -Device(HPBR) { +/* 0:14.7 - SD Controller */ +Device(SDCN) { + Name(_ADR, 0x00140007) +} /* end SDCN */ + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +/* 0:14.1 - Primary (and only) IDE channel */ +Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" +} /* end IDEC */ + +/* 0:14.4 - PCI slot 1, 2, 3 */ +Device(PIBR) { Name(_ADR, 0x00140004) -} /* end HostPciBr */ + Name(_PRW, Package() {0x18, 4}) -Device(ACAD) { - Name(_ADR, 0x00140005) -} /* end Ac97audio */ + Method(_PRT, 0) { + Return (PCIB) + } +} +/* 0:14.6 - GEC Controller */ Device(ACMD) { Name(_ADR, 0x00140006) } /* end Ac97modem */ +#endif Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, @@ -94,12 +81,13 @@ Name(CRES, ResourceTemplate() { 0x0CF8 /* length */ ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x03B0, /* range minimum */ - 0x03DF, /* range maximum */ - 0x0000, /* translation */ - 0x0030 /* length */ + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ 0x0D00, /* range minimum */ @@ -121,13 +109,13 @@ Method(_CRS, 0) { CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, MM1B) ShiftLeft(0x10000000, 4, Local0) Subtract(Local0, TOM1, Local0) @@ -137,13 +125,13 @@ Method(_CRS, 0) { } /* end of Method(_SB.PCI0._CRS) */ /* -* -* FIRST METHOD CALLED UPON BOOT -* -* 1. If debugging, print current OS and ACPI interpreter. -* 2. Get PCI Interrupt routing from ACPI VSM, this -* value is based on user choice in BIOS setup. -*/ + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ Method(_INI, 0) { /* DBGO("\\_SB\\_INI\n") */ /* DBGO(" DSDT.ASL code from ") */ @@ -161,11 +149,9 @@ Method(_INI, 0) { /* Determine the OS we're running on */ CkOT() - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ + /* TODO: It is unstable. */ + //#include "acpi/AmdImc.asl" /* Hudson IMC function */ + //ITZE() /* enable IMC Fan Control*/ } /* End Method(_SB._INI) */ Method(CkOT, 0){ |