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| author | Felix Held <felix-coreboot@felixheld.de> | 2015-05-31 20:28:17 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-20 16:35:47 +0100 |
| commit | d2e8f6ad33c750853844c5674d1a1a926ad7d93a (patch) | |
| tree | fde712f291c184ad279f9c1f4634b49d07eac867 /src/southbridge/amd/agesa/hudson/amd_pci_int_types.h | |
| parent | e536a4d91697fc49d865dfa5065d2cbb31cbc03f (diff) | |
| download | coreboot-d2e8f6ad33c750853844c5674d1a1a926ad7d93a.tar.xz | |
southbridge/amd: add support for Bolton FCH
The Bolton FCH needs different firmware files than the Hudson FCH.
A small patch to vendorcode is probably needed to make the XHCI controller work.
XHCI_DEVID in pci_devs.h is probably wrong for Hudson.
Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/9623
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/amd_pci_int_types.h')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/amd_pci_int_types.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index fafe7ab33e..7b74561f3c 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", |