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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-20 13:24:42 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-20 21:44:16 +0200 |
| commit | cf1f9b6a5bd1be169756dd1cd9568492a880651c (patch) | |
| tree | d451ec4ce232af24145129ad55456d4aed68ec64 /src/southbridge/amd/agesa | |
| parent | 991e951461bc57debc2df82bac76d0ab57682e66 (diff) | |
| download | coreboot-cf1f9b6a5bd1be169756dd1cd9568492a880651c.tar.xz | |
southbridge/hudson: Remove redundant definitions of ACPI IO ports
The ACPI IO ports were defined twice, and used inconsistently. Only
keep one of the definitions for consistency.
Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/agesa')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/early_setup.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.h | 15 |
3 files changed, 7 insertions, 12 deletions
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a1295121ce..d8fdc2792e 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -126,7 +126,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) #if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + u16 tmp = inw(ACPI_PM1_CNT_BLK); tmp = ((tmp & (7 << 10)) >> 10); /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ return (int)tmp; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index cd63c3e814..39dab23d0d 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,7 +40,7 @@ #if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + u16 tmp = inw(ACPI_PM1_CNT_BLK); tmp = ((tmp & (7 << 10)) >> 10); /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ return (int)tmp; diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 683fd2802c..6f757eb72e 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -40,16 +40,6 @@ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define REV_HUDSON_A11 0x11 -#define REV_HUDSON_A12 0x12 - -#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; -#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; -#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; -#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; -#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 - #define ACPI_SMI_CTL_PORT 0xb2 #define ACPI_SMI_CMD_CST_CONTROL 0xde #define ACPI_SMI_CMD_PST_CONTROL 0xad @@ -57,6 +47,11 @@ #define ACPI_SMI_CMD_ENABLE 0xef #define ACPI_SMI_CMD_S4_REQ 0xc0 +#define REV_HUDSON_A11 0x11 +#define REV_HUDSON_A12 0x12 + +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 + #ifndef __SMM__ void pm_write8(u8 reg, u8 value); |