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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 21:20:04 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:29:13 +0200
commit1bcd7fcb6199528fc82685e161d6b39f273a1962 (patch)
tree90e07ca28aa8514375b27b9c638a33701f921d52 /src/southbridge/amd/agesa
parent15279a9696c70b82c2223264a505da9122f9aa7b (diff)
downloadcoreboot-1bcd7fcb6199528fc82685e161d6b39f273a1962.tar.xz
src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Diffstat (limited to 'src/southbridge/amd/agesa')
-rw-r--r--src/southbridge/amd/agesa/hudson/lpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 7be1dc58a3..61dded8e1d 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
interrupt and visit LPC. */
pci_write_config8(dev, 0x78, byte);
- /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
+ /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
byte = pci_read_config8(dev, 0xBB);
byte |= 1 << 0 | 1 << 3;