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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-26 00:57:30 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-06 04:58:40 +0000 |
| commit | 38aff1ad41d6556dbcc466ce11f58ea8ca7a07b7 (patch) | |
| tree | 1f6b554fc1742b373537b642db13488cc8f652f3 /src/southbridge/amd/agesa | |
| parent | 8f39f1f097b8046eb3c80ac1de44ce24ac366560 (diff) | |
| download | coreboot-38aff1ad41d6556dbcc466ce11f58ea8ca7a07b7.tar.xz | |
AGESA f15tn f16kb: Fix ACPI S3 resume for FCH
This recovers FCH configuration on S3 resume path.
Appearst to work, but other defects of HAVE_ACPI_RESUME
must be fixed also before S3 support is re-enabled.
Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/agesa')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/resume.c | 33 |
2 files changed, 28 insertions, 6 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index d870845055..c89f6825f7 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -80,7 +80,6 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); #else void hudson_enable(device_t dev); -void s3_resume_init_data(void *FchParams); #endif /* __PRE_RAM__ */ #endif /* __SMM__ */ diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index cbfa9f421a..e680fadf31 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -20,6 +20,8 @@ #include "hudson.h" #include "AGESA.h" +#include <northbridge/amd/agesa/state_machine.h> + extern FCH_DATA_BLOCK InitEnvCfgDefault; extern FCH_INTERFACE FchInterfaceDefault; extern FCH_RESET_DATA_BLOCK InitResetCfgDefault; @@ -27,13 +29,9 @@ extern FCH_RESET_INTERFACE FchResetInterfaceDefault; #define DUMP_FCH_SETTING 0 -void s3_resume_init_data(void *data) +static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)data; - AMD_CONFIG_PARAMS *StdHeader = FchParams->StdHeader; - *FchParams = InitEnvCfgDefault; - FchParams->StdHeader = StdHeader; FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable; FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable; @@ -120,3 +118,28 @@ void s3_resume_init_data(void *data) } #endif } + +AGESA_STATUS fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader) +{ + FCH_DATA_BLOCK FchParams; + + /* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */ + s3_resume_init_data(&FchParams); + + FchParams.StdHeader = StdHeader; + FchInitS3EarlyRestore(&FchParams); + return AGESA_SUCCESS; +} + +AGESA_STATUS fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader) +{ + FCH_DATA_BLOCK FchParams; + + /* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */ + s3_resume_init_data(&FchParams); + + FchParams.StdHeader = StdHeader; + FchInitS3LateRestore(&FchParams); + + return AGESA_SUCCESS; +} |