diff options
| author | Martin Roth <martin@coreboot.org> | 2019-10-23 21:46:03 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-30 11:16:56 +0000 |
| commit | ff744bf0eee875a03dc98dd6792e3ed0ff4456a0 (patch) | |
| tree | 691260ffe71abac0bb8e2a5607b0d6f1cfb16028 /src/southbridge/amd/amd8111/reset.c | |
| parent | 5331a7cff9ebf6f92542eee53e6556a4d5a0dc75 (diff) | |
| download | coreboot-ff744bf0eee875a03dc98dd6792e3ed0ff4456a0.tar.xz | |
src/southbridge: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/amd8111/reset.c')
| -rw-r--r-- | src/southbridge/amd/amd8111/reset.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index f4907c53da..b175be2727 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -21,7 +21,7 @@ #define PCI_DEV_INVALID (0xffffffffU) -static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_io_locate_device_on_bus(unsigned int pci_id, unsigned int bus) { pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); @@ -41,9 +41,9 @@ static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) void do_board_reset(void) { pci_devfn_t dev; - unsigned bus; - unsigned node = 0; - unsigned link = get_sblk(); + unsigned int bus; + unsigned int node = 0; + unsigned int link = get_sblk(); /* Find the device. * There can only be one 8111 on a hypertransport chain/bus. |