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| author | Jason Schildt <jschildt@gmail.com> | 2005-10-13 00:44:34 +0000 |
|---|---|---|
| committer | Jason Schildt <jschildt@gmail.com> | 2005-10-13 00:44:34 +0000 |
| commit | ab327a3c08a1bd8b33f09827a5f10d91ddb8727d (patch) | |
| tree | 861618c481c5c3f3c421a0cc901dd1a2d66d5dad /src/southbridge/amd/amd8111 | |
| parent | 6ab43fcc48992d46096842b17a00dd51dd835c69 (diff) | |
| download | coreboot-ab327a3c08a1bd8b33f09827a5f10d91ddb8727d.tar.xz | |
- Added explanation of device tree enable.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/amd8111')
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111.c | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_acpi.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_pci.c | 1 |
3 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c index 6f5f1beada..32797041f3 100644 --- a/src/southbridge/amd/amd8111/amd8111.c +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -66,5 +66,8 @@ void amd8111_enable(device_t dev) struct chip_operations southbridge_amd_amd8111_ops = { CHIP_NAME("AMD 8111") + /* This only called when this device is listed in the + * static device tree. + */ .enable_dev = amd8111_enable, }; diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index 46a8e69510..f661ab478e 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -97,6 +97,7 @@ static void acpi_init(struct device *dev) #endif + /* power on after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); @@ -177,6 +178,10 @@ static struct device_operations acpi_ops = { .enable_resources = acpi_enable_resources, .init = acpi_init, .scan_bus = scan_static_bus, + /* We don't need amd8111_enable, chip ops takes care of it. + * It could be useful if these devices were not + * enabled by default. + */ // .enable = amd8111_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/amd/amd8111/amd8111_pci.c b/src/southbridge/amd/amd8111/amd8111_pci.c index 9fe1f98d32..b9a9b3578d 100644 --- a/src/southbridge/amd/amd8111/amd8111_pci.c +++ b/src/southbridge/amd/amd8111/amd8111_pci.c @@ -55,6 +55,7 @@ static struct device_operations pci_ops = { .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, + /* PCI Subordinate bus reset is not implemented */ .ops_pci = &lops_pci, }; |