diff options
author | Julius Werner <jwerner@chromium.org> | 2017-05-18 16:03:26 -0700 |
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committer | Julius Werner <jwerner@chromium.org> | 2017-06-13 20:53:09 +0200 |
commit | 01f9aa5e54cf55ecca1b35185373835e61f10615 (patch) | |
tree | 8cd1ecb517bd948ac2dc2616de789a84a999a911 /src/southbridge/amd/amd8111 | |
parent | d9762f70acc1cc2db5b3905756f5f5a995b9a21a (diff) | |
download | coreboot-01f9aa5e54cf55ecca1b35185373835e61f10615.tar.xz |
Consolidate reset API, add generic reset_prepare mechanism
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/amd/amd8111')
-rw-r--r-- | src/southbridge/amd/amd8111/early_ctrl.c | 4 | ||||
-rw-r--r-- | src/southbridge/amd/amd8111/reset.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index f451003aee..2161669f4f 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -38,7 +38,7 @@ static void enable_cf9(void) enable_cf9_x(sbbusn, sbdn); } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* reset */ @@ -71,7 +71,7 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn) } -void soft_reset(void) +void do_soft_reset(void) { unsigned sblk = get_sblk(); diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index fd2c82ab5b..fea8891a98 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -37,7 +37,7 @@ static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) #include "../../../northbridge/amd/amdk8/reset_test.c" -void hard_reset(void) +void do_hard_reset(void) { pci_devfn_t dev; unsigned bus; |