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authorLi-Ta Lo <ollie@lanl.gov>2004-04-29 20:08:54 +0000
committerLi-Ta Lo <ollie@lanl.gov>2004-04-29 20:08:54 +0000
commit69c5a905ede8053fd2993ed2e4ff14e9970f2dce (patch)
tree0790c872f03deea3d70ad433d58289b123e55aa6 /src/southbridge/amd/amd8131
parentfcdd571aee7592bd3f67283e70fba7608091ba04 (diff)
downloadcoreboot-69c5a905ede8053fd2993ed2e4ff14e9970f2dce.tar.xz
changed dev->enable to dev->enabled. Sorry, I am the only one who can't speak
English in the project. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/amd8131')
-rw-r--r--src/southbridge/amd/amd8131/amd8131_bridge.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
index 44b04d8636..dc474fc7b0 100644
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -98,19 +98,19 @@ static struct pci_driver pcix_driver __pci_driver = {
static void ioapic_enable(device_t dev)
{
uint32_t value;
+
value = pci_read_config32(dev, 0x44);
- if (dev->enable) {
+ if (dev->enabled) {
value |= ((1 << 1) | (1 << 0));
} else {
value &= ~((1 << 1) | (1 << 0));
}
pci_write_config32(dev, 0x44, value);
-//BY LYH
+ /* We have to enable MEM and Bus Master for IOAPIC */
value = pci_read_config32(dev, 0x4);
value |= 6;
pci_write_config32(dev, 0x4, value);
-//BY LYH END
}
static struct device_operations ioapic_ops = {