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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-17 10:56:26 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-23 15:52:09 +0000 |
| commit | a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch) | |
| tree | 4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/southbridge/amd/amd8132 | |
| parent | 9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff) | |
| download | coreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz | |
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/amd8132')
| -rw-r--r-- | src/southbridge/amd/amd8132/bridge.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 52306ab697..162a36129b 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -213,7 +213,7 @@ static void amd8132_pcix_init(struct device *dev) if (chip_rev == 0x01) { /* Errata #37 */ byte = pci_read_config8(dev, 0x0c); - if (byte == 0x08 ) + if (byte == 0x08) pci_write_config8(dev, 0x0c, 0x10); #if 0 @@ -272,7 +272,7 @@ static void amd8132_pcix_init(struct device *dev) /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ dword = pci_read_config32(dev, 0xdc); - dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE + dword |= (1<<1) | (1<<4); // stream disable 1 to 0, DBLINSRATE dword |= (1<<18)|(1<<26); dword &= ~((3<<16)|(3<<24)); pci_write_config32(dev, 0xdc, dword); @@ -385,7 +385,7 @@ static void amd8132_ioapic_init(struct device *dev) } - if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + if ((chip_rev == 0x11) || (chip_rev == 0x12)) { //for b1 b2 /* Errata #73 */ dword = pci_read_config32(dev, 0x80); |