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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-13 17:03:58 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-24 02:09:18 +0000 |
commit | c618b90119171f00886c170b3398a7ce9311d0d6 (patch) | |
tree | 6d43a04cd07026aec535bcf1ecaf4d28fd0fa273 /src/southbridge/amd/cimx/sb700/bootblock.c | |
parent | eb7e6b5c8160f5edfda1ac080ab77c1ba2c48306 (diff) | |
download | coreboot-c618b90119171f00886c170b3398a7ce9311d0d6.tar.xz |
AGESA f15 cimx/sb700: Remove unused chips code
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb700/bootblock.c')
-rw-r--r-- | src/southbridge/amd/cimx/sb700/bootblock.c | 59 |
1 files changed, 0 insertions, 59 deletions
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c deleted file mode 100644 index e10bb05ca9..0000000000 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <arch/io.h> - -static void sb700_enable_rom(void) -{ - u32 word; - u32 dword; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 0x03); - /* SB700 LPC Bridge 0:20:3:44h. - * BIT6: Port Enable for serial port 0x3f8-0x3ff - * BIT29: Port Enable for KBC port 0x60 and 0x64 - * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 - */ - dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30); - /*Turn on all of LPC IO Port decode enable */ - dword = 0xffffffff; - pci_io_write_config32(dev, 0x44, dword); - - /* SB700 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F - * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) - * BIT6: Port Enable for RTC IO 0x70-0x73 - * BIT21: Port Enable for Port 0x80 - */ - dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); - pci_io_write_config32(dev, 0x48, dword); - - /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ - /* Set the 4MB enable bits */ - word = pci_io_read_config16(dev, 0x6c); - word = 0xFFC0; - pci_io_write_config16(dev, 0x6c, word); -} - -static void bootblock_southbridge_init(void) -{ - /* Setup the ROM access for 2M */ - sb700_enable_rom(); -} |