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| author | Stefan Reinauer <reinauer@chromium.org> | 2011-10-31 12:56:45 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-01 19:07:45 +0100 |
| commit | 5ff7c13e858a31addf1558731a12cf6c753b576d (patch) | |
| tree | 82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src/southbridge/amd/cimx/sb800/SBPLATFORM.h | |
| parent | 784544b934d67dc85ccfcf33e04ff148045836ad (diff) | |
| download | coreboot-5ff7c13e858a31addf1558731a12cf6c753b576d.tar.xz | |
remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/SBPLATFORM.h')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index d7317a23a2..db5343dff0 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -20,7 +20,7 @@ * *************************************************************************** * */ - + #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ @@ -112,7 +112,7 @@ typedef union _PCI_ADDR { */ #define SB_CIMx_PARAMETER 0x02 -// Generic +// Generic #define cimSpreadSpectrumDefault TRUE #define cimSpreadSpectrumTypeDefault 0x00 // Normal #define cimHpetTimerDefault TRUE @@ -121,7 +121,7 @@ typedef union _PCI_ADDR { #define cimSpiFastReadEnableDefault 0x01 // Enable #define cimSpiFastReadSpeedDefault 0x01 // 33 MHz #define cimSioHwmPortEnableDefault FALSE -// GPP/AB Controller +// GPP/AB Controller #define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE #define cimResetCpuOnSyncFloodDefault TRUE @@ -129,13 +129,13 @@ typedef union _PCI_ADDR { #define cimGppMemWrImproveDefault TRUE #define cimGppPortAspmDefault FALSE #define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE +#define cimGppPhyPllPowerDownDefault TRUE // USB Controller #define cimUsbPhyPowerDownDefault FALSE // GEC Controller #define cimSBGecDebugBusDefault FALSE #define cimSBGecPwrDefault 0x03 -// Sata Controller +// Sata Controller #define cimSataSetMaxGen2Default 0x00 #define cimSATARefClkSelDefault 0x10 #define cimSATARefDivSelDefault 0x80 @@ -143,11 +143,11 @@ typedef union _PCI_ADDR { #define cimSataPortMultCapDefault TRUE #define cimSataPscCapDefault 0x00 // Enable #define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataFisBasedSwitchingDefault FALSE #define cimSataCccSupportDefault FALSE #define cimSataClkAutoOffDefault FALSE #define cimNativepciesupportDefault FALSE -// Fusion Related +// Fusion Related #define cimAcDcMsgDefault FALSE #define cimTimerTickTrackDefault FALSE #define cimClockInterruptTagDefault FALSE |