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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-01-31 20:32:54 +0200 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-02-04 01:43:31 +0100 |
| commit | fbdbcb713f1f1f184604a3a63e34904ee37a58d9 (patch) | |
| tree | 1ed159166ae2b0f28abb2727454f6433fe7a173a /src/southbridge/amd/cimx/sb800/bootblock.c | |
| parent | d9b5d897d7f05d0ee8f9411628b757beea990b4b (diff) | |
| download | coreboot-fbdbcb713f1f1f184604a3a63e34904ee37a58d9.tar.xz | |
AMD cimx/sb800: Set SPI frequency and prefetch
Broken with/since commit d1cb0eec.
Original intention was to set the frequency for 'Fast Read' command
in bits 15..14, and enable 'Fast Read' command.
Modified register contains SPI frequency for 'Normal Read' command
in bits 13..12. Default for this is 11b for 16.5 MHz. Existing code
unintentionally clears these bits, increasing SPI frequency to 66MHz
for 'Normal Read' command.
This is above specifications for many common SPI flash components
and also makes flashrom older than 0.9.7-r1750 to operate unreliably
on read/write/erase for these platforms.
Change-Id: I30109e2a0410c0bb0bdc968ea71787396b32e761
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5089
Tested-by: build bot (Jenkins)
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/bootblock.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index ac9351e4c2..4fd2739442 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -66,7 +66,6 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { - u8 byte; u32 dword; device_t dev = PCI_DEV(0, 0x14, 0x03); @@ -76,8 +75,8 @@ static void enable_spi_fast_mode(void) pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); // early enable of SPI 33 MHz fast mode read - byte = spi_base[3]; - spi_base[3] = (byte & ~(3 << 14)) | (1 << 14); + dword = spi_base[3]; + spi_base[3] = (dword & ~(3 << 14)) | (1 << 14); spi_base[0] = spi_base[0] | (1 << 18); // fast read enable pci_io_write_config32(dev, 0xa0, save); |