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| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:03:44 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:08:57 +0200 |
| commit | feed329a0c006968242aa3065506b5f37f4308d4 (patch) | |
| tree | 0ef0e9e0c112230dd03fe14e199b0be74776b112 /src/southbridge/amd/cimx/sb800/early.c | |
| parent | 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f (diff) | |
| download | coreboot-feed329a0c006968242aa3065506b5f37f4308d4.tar.xz | |
AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/early.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/early.c | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40a18ccd4c..9d49a52d54 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -24,10 +24,11 @@ #include <arch/io.h> /* inl, outl */ #include <arch/romcc_io.h> /* device_t */ #include "SBPLATFORM.h" -#include "SbEarly.h" +#include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#if CONFIG_RAMINIT_SYSINFO == 1 /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -37,20 +38,23 @@ u32 get_sbdn(u32 bus) { device_t dev; + printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); dev = pci_locate_device_on_bus( PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM), bus); + printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__); return (dev >> 15) & 0x1f; } +#endif /** * @brief South Bridge CIMx romstage entry, * wrapper of sbPowerOnInit entry point. */ -void sb_poweron_init(void) +void sb_Poweron_Init(void) { AMDSBCFG sb_early_cfg; @@ -62,3 +66,17 @@ void sb_poweron_init(void) // VerifyImage() will fail, LocateImage() take minitues to find the image. sbPowerOnInit(&sb_early_cfg); } + +/** + * CIMX not set the clock to 48Mhz until sbBeforePciInit, + * coreboot may need to set this even more earlier + */ +void sb800_clk_output_48Mhz(void) +{ + /* AcpiMMioDecodeEn */ + RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0); + + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ +} + |