diff options
author | Zheng Bao <fishbaozi@gmail.com> | 2012-11-28 11:36:52 +0800 |
---|---|---|
committer | Marc Jones <marcj303@gmail.com> | 2012-11-30 20:03:31 +0100 |
commit | 7bcffa511dee2782702cc2920580d15b34073e1c (patch) | |
tree | 3b3e494d83c6ab44abfd5402f9a98ff970e91f5d /src/southbridge/amd/cimx/sb800/spi.c | |
parent | 78a1667cbc0a26c09079c81aa7b8f4387c5f3774 (diff) | |
download | coreboot-7bcffa511dee2782702cc2920580d15b34073e1c.tar.xz |
AMD S3: Leverage the public SPI routine
Remove the old, unflexible code for storing S3 data in SPI flash.
Refer to flashrom. Tested on Parmer.
Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/spi.c')
-rw-r--r-- | src/southbridge/amd/cimx/sb800/spi.c | 228 |
1 files changed, 67 insertions, 161 deletions
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index e1c2ecb2c4..3b54490117 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -16,201 +16,107 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> #include <arch/io.h> +#include <spi.h> #include <device/device.h> -#include "SBPLATFORM.h" +#include <device/pci.h> +#include <device/pci_ops.h> +static u32 spibar; -void execute_command(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { - *(spi_address + 2) |= 1; + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void wait4command_complete(volatile u8 * spi_address) +static void execute_command(void) { - while (*(spi_address + 2) & 1) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + write8(spibar + 2, read8(spibar + 2) | 1); + + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +void spi_init() { - u8 val; + device_t dev; - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -u8 read_spi_status(volatile u8 * spi_address) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x11; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; + + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; + + readoffby1 = bytesout ? 0 : 1; + + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar + 1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; -} + reset_internal_fifo_pointer(); + execute_command(); -void write_spi_status(volatile u8 * spi_address, u8 status) -{ - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + reset_internal_fifo_pointer(); + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void spi_write_disable(volatile u8 * spi_address) +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } |