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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-02-07 17:38:45 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-02-14 22:37:59 +0100
commit24501cae529a51ab9304721be0ec60384ab81ee0 (patch)
tree0317f32ac6174b914b0e4400e63fd64f392059ee /src/southbridge/amd/cimx/sb800
parent41cd047cd25b5fbb02da3e37b9dc2ca6ca90e34e (diff)
downloadcoreboot-24501cae529a51ab9304721be0ec60384ab81ee0.tar.xz
AMD cimx/sb800: Initially enable all GPP ports
PCIe root ports on devices 0:15.0 to 0:15.3 should at first all appear visible in hardware. The real configuration will be done by vendorcode once we call sb_Before_Pci_Init(). Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8387 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800')
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c19
1 files changed, 2 insertions, 17 deletions
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 9a08121d54..510bf234fb 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -266,6 +266,8 @@ static void sb800_init(void *chip_info)
{
sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
sb800_cimx_config(sb_config);
+
+ abcfg_reg(0xc0, 0x01FF, 0x0F4);
}
/**
@@ -339,23 +341,6 @@ static void sb800_enable(device_t dev)
switch (dev->path.pci.devfn) {
case (0x11 << 3) | 0: /* 0:11.0 SATA */
- /* the first sb800 device */
- switch (GPP_CFGMODE) { /* config the GPP PCIe ports */
- case GPP_CFGMODE_X2200:
- abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */
- break;
- case GPP_CFGMODE_X2110:
- abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */
- break;
- case GPP_CFGMODE_X1111:
- abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */
- break;
- case GPP_CFGMODE_X4000:
- default:
- abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */
- break;
- }
-
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)