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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-01-03 10:23:28 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-07 10:28:59 +0000 |
| commit | 0f8b8d920c2f060bbe7a9139fde823e3b2e875d7 (patch) | |
| tree | 8d53a881ad95ab6a4e9e5ded8622d99fd2b0b360 /src/southbridge/amd/cimx/sb900/late.c | |
| parent | f212cf3506a9ad3d699a4afe148bfd554932f7b8 (diff) | |
| download | coreboot-0f8b8d920c2f060bbe7a9139fde823e3b2e875d7.tar.xz | |
src: Move constant to the right side of comparison
Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/27015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900/late.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/late.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 9a2f837010..25e087f641 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -354,9 +354,9 @@ static void sb900_enable(struct device *dev) case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = ENABLED; - if (1 == sb_chip->boot_switch_sata_ide) + if (sb_chip->boot_switch_sata_ide == 1) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. - else if (0 == sb_chip->boot_switch_sata_ide) + else if (sb_chip->boot_switch_sata_ide == 0) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { sb_config->SATAMODE.SataMode.SataController = DISABLED; |