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author | efdesign98 <efdesign98@gmail.com> | 2011-06-20 19:56:06 -0700 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-06-28 23:09:25 +0200 |
commit | 7c0c64e1033b4edf9a488e8e31948726ee17465e (patch) | |
tree | 17d6b727807ed513c68ac00b9255577a86717b1b /src/southbridge/amd/cimx/sb900/smbus.h | |
parent | 7c634ae8c18d1e311b5b96f09b5e6af23e57eaf7 (diff) | |
download | coreboot-7c0c64e1033b4edf9a488e8e31948726ee17465e.tar.xz |
Addition of Family12/SB900 wrapper code
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.
Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900/smbus.h')
-rwxr-xr-x | src/southbridge/amd/cimx/sb900/smbus.h | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h new file mode 100755 index 0000000000..e6ade1ed48 --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/smbus.h @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB900_SMBUS_H_ +#define _SB900_SMBUS_H_ + +//#include <stdint.h> + +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif |