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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-02 18:00:29 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-04 15:08:03 +0000 |
| commit | 065857ee7fd61b05025d7a803e82f2b9b53cbc9a (patch) | |
| tree | 3016bedfeac37b6aca649f1474f6343228ae9673 /src/southbridge/amd/cimx/sb900 | |
| parent | bdaec07a859c0c05e7fd5276a15b3933da574368 (diff) | |
| download | coreboot-065857ee7fd61b05025d7a803e82f2b9b53cbc9a.tar.xz | |
arch/io.h: Drop unnecessary include
Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900')
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/bootblock.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/reset.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 734cc7a831..11faeab3d7 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> static void sb900_enable_rom(void) diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 4b96d3c8c0..787f7426ce 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -16,7 +16,6 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <arch/io.h> #include <device/pci_ops.h> #include <cf9_reset.h> #include <reset.h> |