diff options
| author | Tobias Diedrich <ranma+coreboot@tdiedrich.de> | 2015-06-15 01:59:03 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-24 00:21:01 +0200 |
| commit | 0dab6d192bd29590ae88c63504396ef649c110bd (patch) | |
| tree | 02a9770438858e09df0ef9a116bd27d62d3a333b /src/southbridge/amd/cimx | |
| parent | a4d179af562770d17ab92dc57f7104fd78be75ba (diff) | |
| download | coreboot-0dab6d192bd29590ae88c63504396ef649c110bd.tar.xz | |
amd/sb800: Make UsbRxMode per-board customizable
On my Foxconn nT-A3500 on cold boot the board doesn't survive the soft
reboot in the UsbRxMode path and the vendor bios doesn't touch this
Cg2Pll voltage setting either.
The fixup code for UsbRxMode in src/vendorcode/amd/cimx/sb800/SBPort.c
doesn't seem to "CG PLL multiplier for USB Rx 1.1 mode", but rather
lowers the Cg2Pll voltage from the hw default of 1.222V to 1.1V
by setting Cg2Pll_IVR_TRIM in CGPllConfig5 to 1000.
See also USB_PLL_Voltage which is only used in the UsbRxMode code path.
However if this is already the efuse/eprom default for the SB800 then
UsbRxMode is a no-op, so whether or not it gets executed depends on the
very exact hw revision of the southbridge chip and could change between
two instances of the same board.
UsbRxMode used to be unitialized and was first set to default to 1
in http://review.coreboot.org/6474 (change I32237ff9,
southbridge/amd/cimx/sb800: Uninitialized variables in config func):
> > Why initialize those to 1? (just curious)
> See src/vendorcode/amd/cimx/sb800/SBTYPE.h
> git grep 'SbSpiSpeedSupport\|UsbRxMode'
> src/vendorcode/amd/cimx/sb800/SBTYPE.h
I could not find a corresponding errata in the SB800 errata list,
however errata 15 (USB Resets Asynchronously With Port CF9h Hard Reset)
might play into this being unsafe to do since the code uses CF9h to
reset.
So its possible that while previously undefined it still ended up
defaulting to 0 and the codepath exercised on my board is simply
buggy or there is a difference between a true "SB800" and the
"A50 Hudson M1" presumably used on my board.
Change-Id: I33f45925e222b86c0a97ece48f1ba97f6f878499
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10549
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/cimx')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/cfg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 9a3ca3a967..a3e69fcc87 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->USBMODE.UsbModeReg = USB_CONFIG; sb_config->SbUsbPll = 0; /* CG PLL multiplier for USB Rx 1.1 mode (0=disable, 1=enable) */ - sb_config->UsbRxMode = 1; + sb_config->UsbRxMode = USB_RX_MODE; /* SATA */ sb_config->SataClass = SATA_MODE; |