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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-01 13:43:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-01 20:32:15 +0000 |
| commit | f1b58b78351d7ed220673e688a2f7bc9e96da4e2 (patch) | |
| tree | d8aae223f0e426f189cb4750b972a31e09d46b88 /src/southbridge/amd/cimx | |
| parent | 44e89af6e609874f2f18d30f1e66dce8b5a98eff (diff) | |
| download | coreboot-f1b58b78351d7ed220673e688a2f7bc9e96da4e2.tar.xz | |
device/pci: Fix PCI accessor headers
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/amd/cimx')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/fan.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/lpc.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/reset.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/bootblock.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/lpc.c | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/reset.c | 1 |
8 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 585d5a8f87..dae8df8288 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> static void enable_rom(void) { diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index db87b6ac87..a8dfa31d9a 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -16,6 +16,7 @@ #include <southbridge/amd/cimx/cimx_util.h> #include <device/device.h> #include <device/pci.h> /* device_operations */ +#include <device/pci_ops.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index c66206f55c..872e045a1d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -17,6 +17,7 @@ #include <device/device.h> #include <device/pci.h> /* device_operations */ +#include <device/pci_ops.h> #include <device/pci_ids.h> #include <bootstate.h> #include <arch/ioapic.h> diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 2759af6488..8573f6fafe 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,6 +20,7 @@ #include <arch/ioapic.h> #include "lpc.h" #include <arch/io.h> +#include <device/pci_ops.h> void lpc_read_resources(struct device *dev) { diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index db0aebb9ee..4b96d3c8c0 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <cf9_reset.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index a06946352c..734cc7a831 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> static void sb900_enable_rom(void) { diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 64b6aa51de..b04ecfa123 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -14,6 +14,7 @@ */ #include <device/pci.h> +#include <device/pci_ops.h> #include "lpc.h" #include <console/console.h> /* printk */ #include <arch/ioapic.h> diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index db0aebb9ee..4b96d3c8c0 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <cf9_reset.h> #include <reset.h> |