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authorMartin Roth <martinroth@google.com>2017-06-24 21:30:14 -0600
committerMartin Roth <martinroth@google.com>2017-06-30 03:44:59 +0000
commit083504b66b5f3b281221f0a8f4fd62a4d9071287 (patch)
treedcf6fcb31f5d7ee760634c86b0fc06a7383e6d94 /src/southbridge/amd/cimx
parent5f9c6734fc9bbe69c007c46c8ec6f314bd5522a8 (diff)
downloadcoreboot-083504b66b5f3b281221f0a8f4fd62a4d9071287.tar.xz
southbridge/amd: add IS_ENABLED() around Kconfig symbol references
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx')
-rw-r--r--src/southbridge/amd/cimx/sb700/Platform.h2
-rw-r--r--src/southbridge/amd/cimx/sb800/SBPLATFORM.h5
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c2
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c6
-rw-r--r--src/southbridge/amd/cimx/sb900/early.c4
5 files changed, 8 insertions, 11 deletions
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 7476cb96fa..08cff4ad71 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -59,7 +59,7 @@ void TraceCode ( UINT32 Level, UINT32 Code);
#ifdef TRACE
#undef TRACE
#endif
- #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
+ #if IS_ENABLED(CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL)
#define TRACE(Arguments) printk Arguments
#else
#define TRACE(Arguments) do {} while (0)
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index c933207179..75cf12b099 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -49,7 +49,7 @@ typedef union _PCI_ADDR {
#endif
#define FIXUP_PTR(ptr) ptr
-#if CONFIG_SB800_IMC_FWM
+#if IS_ENABLED(CONFIG_SB800_IMC_FWM)
#define IMC_ENABLE_OVER_WRITE 0x01
#endif
@@ -153,10 +153,7 @@ typedef union _PCI_ADDR {
#define cimFusionMsgCStageDefault FALSE
#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
-
-#if CONFIG_HAVE_ACPI_RESUME
#include <spi-generic.h>
-#endif
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 008a19b11e..585d5a8f87 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -99,7 +99,7 @@ static void enable_clocks(void)
// change twice.
reg32 = *acpi_mmio;
reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)
-#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK
+#if !IS_ENABLED(CONFIG_SUPERIO_WANTS_14MHZ_CLOCK)
reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz
#endif
*acpi_mmio = reg32;
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index f4b1769f9a..6b3af0ef58 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -372,7 +372,7 @@ static void sb800_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
clear_ioapic(VIO_APIC_VADDR);
-#if CONFIG_CPU_AMD_AGESA
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
#else
@@ -406,9 +406,9 @@ static void sb800_enable(device_t dev)
case (0x14 << 3) | 3: /* 0:14:3 LPC */
/* Initialize the fans */
-#if CONFIG_SB800_IMC_FAN_CONTROL
+#if IS_ENABLED(CONFIG_SB800_IMC_FAN_CONTROL)
init_sb800_IMC_fans(dev);
-#elif CONFIG_SB800_MANUAL_FAN_CONTROL
+#elif IS_ENABLED(CONFIG_SB800_MANUAL_FAN_CONTROL)
init_sb800_MANUAL_fans(dev);
#endif
break;
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index bee7d74141..1f787f90b2 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -96,7 +96,7 @@ void sb_before_pci_init(void)
void sb_After_Pci_Init(void)
{
-#if !CONFIG_BOARD_AMD_DINAR
+#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
AMDSBCFG sb_early_cfg;
printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
@@ -128,7 +128,7 @@ void sb_Mid_Post_Init(void)
void sb_Late_Post(void)
{
-#if !CONFIG_BOARD_AMD_DINAR
+#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
AMDSBCFG sb_early_cfg;
u8 data;