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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 21:20:04 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:29:13 +0200
commit1bcd7fcb6199528fc82685e161d6b39f273a1962 (patch)
tree90e07ca28aa8514375b27b9c638a33701f921d52 /src/southbridge/amd/cimx
parent15279a9696c70b82c2223264a505da9122f9aa7b (diff)
downloadcoreboot-1bcd7fcb6199528fc82685e161d6b39f273a1962.tar.xz
src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Diffstat (limited to 'src/southbridge/amd/cimx')
-rw-r--r--src/southbridge/amd/cimx/sb700/bootblock.c4
-rw-r--r--src/southbridge/amd/cimx/sb800/Kconfig2
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c4
-rw-r--r--src/southbridge/amd/cimx/sb900/bootblock.c4
4 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 3cf647b8f2..2f67a36106 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -45,7 +45,7 @@ static void sb700_enable_rom(void)
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
/* Set the 4MB enable bits */
word = pci_io_read_config16(dev, 0x6c);
word = 0xFFC0;
@@ -54,6 +54,6 @@ static void sb700_enable_rom(void)
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
+ /* Setup the ROM access for 2M */
sb700_enable_rom();
}
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 78be023c5d..5748f790c8 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -214,7 +214,7 @@ config SB800_IMC_FAN_CONTROL
depends on SB800_IMC_FWM
help
Set up the SB800 to use the IMC based Fan controller. This requires
- the IMC rom from AMD. Configure the registers in devicetree.cb.
+ the IMC ROM from AMD. Configure the registers in devicetree.cb.
endchoice
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index cbf6918411..89e56b6505 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -44,7 +44,7 @@ static void enable_rom(void)
dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
pci_io_write_config32(dev, 0x48, dword);
- /* Enable rom access */
+ /* Enable ROM access */
word = pci_io_read_config16(dev, 0x6c);
word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
pci_io_write_config16(dev, 0x6c, word);
@@ -107,7 +107,7 @@ static void enable_clocks(void)
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
+ /* Setup the ROM access for 2M */
enable_rom();
enable_prefetch();
enable_spi_fast_mode();
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index cf81724b3c..50d3087641 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -44,7 +44,7 @@ static void sb900_enable_rom(void)
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
/* Set the 4MB enable bits */
word = pci_io_read_config16(dev, 0x6c);
word = 0xFFC0;
@@ -53,6 +53,6 @@ static void sb900_enable_rom(void)
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
+ /* Setup the ROM access for 2M */
sb900_enable_rom();
}