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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-28 14:14:52 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-04 16:41:49 +0000
commit08cd65198e44a5c26ba8f1f5439fbf7475fb0ed0 (patch)
tree9c07978b28062b7d650698f71360fe54262157c4 /src/southbridge/amd/cimx
parent8cee45c3f8f05d936ba181f56405b8c936666a36 (diff)
downloadcoreboot-08cd65198e44a5c26ba8f1f5439fbf7475fb0ed0.tar.xz
sb/amd/cimx/sb800: add C bootblock southbridge initialization
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37329 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx')
-rw-r--r--src/southbridge/amd/cimx/sb800/Makefile.inc4
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c23
2 files changed, 23 insertions, 4 deletions
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 418110b5e0..ccb3a2a744 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -16,6 +16,10 @@
# SB800 Platform Files
+ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
+bootblock-y += bootblock.c
+endif
+
romstage-y += cfg.c
romstage-y += early.c
romstage-y += smbus.c smbus_spd.c
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 28b37c30f4..b4f03dad7e 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -79,18 +79,21 @@ static void enable_spi_fast_mode(void)
pci_io_write_config32(dev, 0xa0, save);
}
-static void enable_clocks(void)
+static void enable_acpimmio_decode_pm24(void)
{
u8 reg8;
- u32 reg32;
- volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
- // Program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(reg8, 0xCD7);
+}
+
+static void enable_clocks(void)
+{
+ u32 reg32;
+ volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
// Program SB800 MiscClkCntrl register to configure clock output on the
// 14M_25M_48M_OSC ball usually used for the Super-I/O.
@@ -112,5 +115,17 @@ static void bootblock_southbridge_init(void)
enable_rom();
enable_prefetch();
enable_spi_fast_mode();
+
+ // Program AcpiMmioEn to enable MMIO access to MiscCntrl register
+ enable_acpimmio_decode_pm24();
enable_clocks();
}
+
+#if !CONFIG(ROMCC_BOOTBLOCK)
+#include <bootblock_common.h>
+
+void bootblock_soc_early_init(void)
+{
+ bootblock_southbridge_init();
+}
+#endif