summaryrefslogtreecommitdiff
path: root/src/southbridge/amd/cs5530/chip.h
diff options
context:
space:
mode:
authorUwe Hermann <uwe@hermann-uwe.de>2007-09-14 00:09:29 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-09-14 00:09:29 +0000
commit3335adb771c5e6bf2fb200285a8af7134446bb71 (patch)
tree60a70d32b72273e6d32736aa3b2e871b5500c393 /src/southbridge/amd/cs5530/chip.h
parent741e1e658f060435cfd5505f96cab55045a889d5 (diff)
downloadcoreboot-3335adb771c5e6bf2fb200285a8af7134446bb71.tar.xz
This is a full rewrite of all the CS5530/CS5530A code. The previous code was
mostly undocumented, had a broken coding style, contained lots of dead code and had several other problems, e.g. it enabled write access to the ROM (why?), it unconditionally enabled primary/secondary IDE (which should have a config option) and that even _twice_ (which is um... wrong). The new code - has 'ide0_enable' and 'ide1_enable' config options (which actually work) to enable/disable the primary/secondary IDE interface in Config.lb. - Does _not_ enable write access to the ROM (or is there some good reason to do that? If so, it should at least have a config option). - Contains a bit more documentation. - Uses readable (and documented) #defines instead of hardcoded magic values. - aaand... it actually compiles ;-) Yep, that's right. The previous code wouldn't even build, as it hadn't been fully ported from v1 (still used v1 functions which are simply not available in v2). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5530/chip.h')
-rw-r--r--src/southbridge/amd/cs5530/chip.h31
1 files changed, 25 insertions, 6 deletions
diff --git a/src/southbridge/amd/cs5530/chip.h b/src/southbridge/amd/cs5530/chip.h
index ed891b2acc..f7ce004530 100644
--- a/src/southbridge/amd/cs5530/chip.h
+++ b/src/southbridge/amd/cs5530/chip.h
@@ -1,12 +1,31 @@
-#ifndef _SOUTHBRIDGE_AMD_CS5530
-#define _SOUTHBRIDGE_AMD_CS5530
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_AMD_CS5530_CHIP_H
+#define SOUTHBRIDGE_AMD_CS5530_CHIP_H
extern struct chip_operations southbridge_amd_cs5530_ops;
struct southbridge_amd_cs5530_config {
- /* PCI function enables so the pci scan bus finds the devices */
- int enable_ide;
- int enable_nvram;
+ int ide0_enable:1;
+ int ide1_enable:1;
};
-#endif /* _SOUTHBRIDGE_AMD_CS5530 */
+#endif /* SOUTHBRIDGE_AMD_CS5530_CHIP_H */