summaryrefslogtreecommitdiff
path: root/src/southbridge/amd/cs5530/cs5530.c
diff options
context:
space:
mode:
authorarch import user (historical) <svn@openbios.org>2005-07-06 17:06:46 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 17:06:46 +0000
commitd24d6993b6d7bcf7977d74d081e718e1b076d1b0 (patch)
treea699baad12aa9f044a10fac2658cd730c5891886 /src/southbridge/amd/cs5530/cs5530.c
parent4e83d70a4393674ac3b54d1343533fc1d2c489d0 (diff)
downloadcoreboot-d24d6993b6d7bcf7977d74d081e718e1b076d1b0.tar.xz
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26
Creator: Hamish Guthrie <hamish@prodigi.ch> Added AMD GX1 northbridge and cs5530 Southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5530/cs5530.c')
-rw-r--r--src/southbridge/amd/cs5530/cs5530.c92
1 files changed, 92 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5530/cs5530.c b/src/southbridge/amd/cs5530/cs5530.c
new file mode 100644
index 0000000000..f70918e566
--- /dev/null
+++ b/src/southbridge/amd/cs5530/cs5530.c
@@ -0,0 +1,92 @@
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "cs5530.h"
+
+static void nvram_on(struct device *dev)
+{
+#if 0
+ volatile char *flash = (volatile unsigned char *)0xFFFc0000;
+ unsigned char id1, id2;
+#endif
+ unsigned char reg;
+
+ /* Enable writes to flash at top of memory */
+ pci_write_config8(dev, 0x52, 0xee);
+
+ /* Set positive decode on ROM */
+ /* Also, there is no apparent reason to turn off the devoce on the */
+ /* IDE devices */
+
+ reg = pci_read_config8(dev, 0x5b);
+ reg |= 1 << 5; /* ROM Decode */
+ reg |= 1 << 3; /* Primary IDE decode */
+ reg |= 1 << 4; /* Secondary IDE decode */
+
+ pci_write_config8(dev, 0x5b, reg);
+
+#if 0 // just to test if the flash is accessible!
+ *(flash + 0x555) = 0xaa;
+ *(flash + 0x2aa) = 0x55;
+ *(flash + 0x555) = 0x90;
+
+ id1 = *(volatile unsigned char *) flash;
+ id2 = *(volatile unsigned char *) (flash + 1);
+
+ *flash = 0xf0;
+
+ printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
+#endif
+}
+
+
+static void southbridge_init(struct device *dev)
+{
+ printk_spew("cs5530: %s\n", __FUNCTION__);
+ nvram_on(dev);
+}
+
+/*
+static void dump_south(struct device *dev)
+{
+ int i, j;
+
+ for(i=0; i<256; i+=16) {
+ printk_debug("0x%02x: ", i);
+ for(j=0; j<16; j++)
+ printk_debug("%02x ", pci_read_config8(dev, i+j));
+ printk_debug("\n");
+ }
+}
+*/
+
+static void southbridge_enable(struct device *dev)
+{
+ printk_spew("%s: dev is %p\n", __FUNCTION__, dev);
+}
+
+static void cs5530_pci_dev_enable_resources(device_t dev)
+{
+ printk_spew("cs5530.c: %s()\n", __FUNCTION__);
+ pci_dev_enable_resources(dev);
+ enable_childrens_resources(dev);
+}
+
+static struct device_operations southbridge_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = cs5530_pci_dev_enable_resources,
+ .init = southbridge_init,
+ .enable = southbridge_enable,
+ .scan_bus = scan_static_bus,
+};
+
+static struct pci_driver cs5530_pci_driver __pci_driver = {
+ .ops = &southbridge_ops,
+ .vendor = PCI_VENDOR_ID_CYRIX,
+ .device = PCI_DEVICE_ID_CYRIX_5530_LEGACY,
+};