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| author | Richard Smith <smithbone@gmail.com> | 2006-08-25 05:01:30 +0000 |
|---|---|---|
| committer | Richard Smith <smithbone@gmail.com> | 2006-08-25 05:01:30 +0000 |
| commit | 59ba228f921169bb12347932237c7500ccd58b41 (patch) | |
| tree | 3f044b86c34ff6fd843dcebe5e62b29afdfab0d4 /src/southbridge/amd/cs5536/chip.h | |
| parent | 689c1448392ed93dfafc51a2dba39ba37631ce29 (diff) | |
| download | coreboot-59ba228f921169bb12347932237c7500ccd58b41.tar.xz | |
- Added suport for enabling USB P4 on the olpc
USB P4 is disabled by default and we need to setup the mux bits proper
to make it work. This is the frame work for that. All thats needed
is the right address values
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/chip.h')
| -rw-r--r-- | src/southbridge/amd/cs5536/chip.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index 1edb349ac7..6bd87430fd 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -12,6 +12,7 @@ struct southbridge_amd_cs5536_config { int enable_gpio0_inta; /* almost always will be true */ int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */ int enable_uarta; /* internal uarta interrupt enable */ + int enable_USBP4_host; /* Enable USB Port 4 as a host */ /* following are IRQ numbers for various southbridge resources. */ /* I have guessed at some things, as I still don't have an lspci from anyone */ int ide_irq; /* f.2 */ |