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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-05-16 02:51:16 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-05-16 02:51:16 +0000 |
| commit | 5d573c28e7520085ff7b687c05834292d615860a (patch) | |
| tree | c57d0b36b4b1bd793a847c94352b6efee88c261e /src/southbridge/amd/cs5536/chip.h | |
| parent | 98e904ea7cfe9ef1ffeda4d3eaac2d42a5345760 (diff) | |
| download | coreboot-5d573c28e7520085ff7b687c05834292d615860a.tar.xz | |
Commit for IDE NAND FLASH
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/chip.h')
| -rw-r--r-- | src/southbridge/amd/cs5536/chip.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index cb3cbe1039..12cfecbd72 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -8,6 +8,7 @@ struct southbridge_amd_cs5536_config { int lpc_serirq_enable; /* how to enable, e.g. 0x80 */ int lpc_irq; /* what to enable, e.g. 0x18 */ int enable_gpio0_inta; /* almost always will be true */ + int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */ }; #endif /* _SOUTHBRIDGE_AMD_CS5536 */ |