diff options
author | Jordan Crouse <jordan.crouse@amd.com> | 2007-05-10 18:43:57 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2007-05-10 18:43:57 +0000 |
commit | 2a133f7851dd819fe4d99adebbd8fb4c173ae579 (patch) | |
tree | d5a88891cb9be24ecff61054fee49115fd5cfa4a /src/southbridge/amd/cs5536/cs5536.c | |
parent | 9934b813da2556ab8159cfc13fb993ae98b04db4 (diff) | |
download | coreboot-2a133f7851dd819fe4d99adebbd8fb4c173ae579.tar.xz |
Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/cs5536.c')
-rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 303 |
1 files changed, 157 insertions, 146 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index e4d81abc68..afbec24a39 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -41,23 +41,23 @@ struct msrinit { /* Master Configuration Register for Bus Masters.*/ struct msrinit SB_MASTER_CONF_TABLE[] = { - {USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000}}, - {AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000}}, - {0,{0,0}} + {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, + {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}}, + {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, + {MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}}, + {0, {0, 0}} }; /* 5536 Clock Gating*/ struct msrinit CS5536_CLOCK_GATING_TABLE[] = { -/* MSR Setting*/ - {GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - {GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - {MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/ - {ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {0,{0,0}} + /* MSR Setting*/ + {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, + {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, + {GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, + {MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */ + {ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, + {AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, + {0, {0, 0}} }; struct acpiinit { @@ -73,24 +73,24 @@ struct acpiinit acpi_init_table[] = { {ACPI_IO_BASE + 0x18, 0x0FFFFFFFF}, {ACPI_IO_BASE + 0x00, 0x0000FFFF}, {PMS_IO_BASE + PM_SCLK, 0x000000E00}, - {PMS_IO_BASE + PM_SED, 0x000004601}, + {PMS_IO_BASE + PM_SED, 0x000004601}, {PMS_IO_BASE + PM_SIDD, 0x000008C02}, - {PMS_IO_BASE + PM_WKD, 0x0000000A0}, + {PMS_IO_BASE + PM_WKD, 0x0000000A0}, {PMS_IO_BASE + PM_WKXD, 0x0000000A0}, - {0,0,0} + {0, 0, 0} }; struct FLASH_DEVICE { - unsigned char fType; /* Flash type: NOR or NAND */ + unsigned char fType; /* Flash type: NOR or NAND */ unsigned char fInterface; /* Flash interface: I/O or Memory */ - unsigned long fMask; /* Flash size/mask */ + unsigned long fMask; /* Flash size/mask */ }; struct FLASH_DEVICE FlashInitTable[] = { - { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */ - { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */ - { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */ - { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */ + {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ + {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ + {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ + {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ }; #define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0])) @@ -100,8 +100,7 @@ uint32_t FlashPort[] = { MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, MDD_LBAR_FLSH3 - }; - +}; /* ***************************************************************************/ /* **/ @@ -110,39 +109,39 @@ uint32_t FlashPort[] = { /* * Program ACPI LBAR and initialize ACPI registers.*/ /* **/ /* ***************************************************************************/ -static void pmChipsetInit(void) { +static void pmChipsetInit(void) +{ uint32_t val = 0; uint16_t port; - port = (PMS_IO_BASE + 0x010); - val = 0x0E00 ; /* 1ms*/ + port = (PMS_IO_BASE + 0x010); + val = 0x0E00; /* 1ms */ outl(val, port); - /* PM_WKXD*/ - /* Make sure bits[3:0]=0000b to clear the*/ - /* saved Sx state*/ - port = (PMS_IO_BASE + 0x034); - val = 0x0A0 ; /* 5ms*/ + /* PM_WKXD */ + /* Make sure bits[3:0]=0000b to clear the */ + /* saved Sx state */ + port = (PMS_IO_BASE + 0x034); + val = 0x0A0; /* 5ms */ outl(val, port); - /* PM_WKD*/ - port = (PMS_IO_BASE + 0x030); + /* PM_WKD */ + port = (PMS_IO_BASE + 0x030); outl(val, port); - /* PM_SED*/ - port = (PMS_IO_BASE + 0x014); + /* PM_SED */ + port = (PMS_IO_BASE + 0x014); /* mov eax, 0x057642 ; 100ms, works*/ - val = 0x04601 ; /* 5ms*/ + val = 0x04601; /* 5ms */ outl(val, port); - /* PM_SIDD*/ - port = (PMS_IO_BASE + 0x020); + /* PM_SIDD */ + port = (PMS_IO_BASE + 0x020); /* mov eax, 0x0AEC84 ; 200ms, works*/ - val = 0x08C02 ; /* 10ms*/ + val = 0x08C02; /* 10ms */ outl(val, port); } - /*************************************************************************** * * ChipsetFlashSetup @@ -152,7 +151,8 @@ static void pmChipsetInit(void) { * configured (don't call it if you want IDE). * **************************************************************************/ -static void ChipsetFlashSetup(void){ +static void ChipsetFlashSetup(void) +{ msr_t msr; int i; int numEnabled = 0; @@ -173,13 +173,15 @@ static void ChipsetFlashSetup(void){ else msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; - printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); + printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], + msr.hi, msr.lo); wrmsr(FlashPort[i], msr); /* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); - printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); + printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, + msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr); /* update the number enabled */ @@ -190,24 +192,26 @@ static void ChipsetFlashSetup(void){ printk_debug("ChipsetFlashSetup: Finish\n"); } + /* ***************************************************************************/ /* **/ /* * enable_ide_nand_flash_header */ /* Run after VSA init to enable the flash PCI device header */ /* **/ /* ***************************************************************************/ -static void enable_ide_nand_flash_header(){ - /* Tell VSA to use FLASH PCI header. Not IDE header.*/ +static void enable_ide_nand_flash_header() +{ + /* Tell VSA to use FLASH PCI header. Not IDE header. */ outl(0x80007A40, 0xCF8); outl(0xDEADBEEF, 0xCFC); } - #define RTC_CENTURY 0x32 #define RTC_DOMA 0x3D #define RTC_MONA 0x3E -static void lpc_init(struct southbridge_amd_cs5536_config *sb){ +static void lpc_init(struct southbridge_amd_cs5536_config *sb) +{ msr_t msr; if (sb->lpc_serirq_enable) { @@ -216,7 +220,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb){ wrmsr(MDD_IRQM_LPC, msr); if (sb->lpc_serirq_polarity) { msr.lo = sb->lpc_serirq_polarity << 16; - msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */ + msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */ msr.hi = 0; wrmsr(MDD_LPC_SIRQ, msr); } @@ -246,43 +250,44 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb){ isa_dma_init(); } - -static void uarts_init(struct southbridge_amd_cs5536_config *sb){ +static void uarts_init(struct southbridge_amd_cs5536_config *sb) +{ msr_t msr; uint16_t addr; uint32_t gpio_addr; device_t dev; - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_ISA, 0); gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - gpio_addr &= ~1; /* clear IO bit */ + gpio_addr &= ~1; /* clear IO bit */ printk_debug("GPIO_ADDR: %08X\n", gpio_addr); /* This could be extended to support IR modes */ /* COM1 */ - if (sb->com1_enable){ + if (sb->com1_enable) { /* Set the address */ - switch (sb->com1_address){ - case 0x3F8: + switch (sb->com1_address) { + case 0x3F8: addr = 7; break; - case 0x3E8: + case 0x3E8: addr = 6; break; - case 0x2F8: + case 0x2F8: addr = 5; break; - case 0x2E8: + case 0x2E8: addr = 4; break; } msr = rdmsr(MDD_LEG_IO); msr.lo |= addr << 16; - wrmsr(MDD_LEG_IO,msr); + wrmsr(MDD_LEG_IO, msr); /* Set the IRQ */ msr = rdmsr(MDD_IRQM_YHIGH); @@ -301,8 +306,9 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){ /* Set: INAUX1 Select (0x34) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - /* Set: GPIO 8 + 9 Pull Up (0x18) */ - outl(GPIOL_8_SET | GPIOL_9_SET, gpio_addr + GPIOL_PULLUP_ENABLE); + /* Set: GPIO 8 + 9 Pull Up (0x18) */ + outl(GPIOL_8_SET | GPIOL_9_SET, + gpio_addr + GPIOL_PULLUP_ENABLE); /* enable COM1 */ /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ @@ -310,47 +316,45 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){ msr.hi = 0; wrmsr(MDD_UART1_CONF, msr); - } - else{ + } else { /* Reset and disable COM1 */ printk_err("Not disabling COM1 due to a bug ...\n"); /* for now, don't do this! */ return; msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; // reset + msr.lo = 1; // reset wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; // disabled wrmsr(MDD_UART1_CONF, msr); /* Disable the IRQ */ msr = rdmsr(MDD_LEG_IO); msr.lo |= ~(0xF << 16); - wrmsr(MDD_LEG_IO,msr); + wrmsr(MDD_LEG_IO, msr); } /* COM2 */ - if (sb->com2_enable){ - switch (sb->com2_address){ - case 0x3F8: + if (sb->com2_enable) { + switch (sb->com2_address) { + case 0x3F8: addr = 7; break; - case 0x3E8: + case 0x3E8: addr = 6; break; - case 0x2F8: + case 0x2F8: addr = 5; break; - case 0x2E8: + case 0x2E8: addr = 4; break; } msr = rdmsr(MDD_LEG_IO); msr.lo |= addr << 20; - wrmsr(MDD_LEG_IO,msr); - + wrmsr(MDD_LEG_IO, msr); /* Set the IRQ */ msr = rdmsr(MDD_IRQM_YHIGH); @@ -361,7 +365,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){ /* Set: Output Enable (0x4) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_3_SET,gpio_addr + GPIOL_OUT_AUX1_SELECT); + outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); /* GPIO4 - UART2_TX */ /* Set: Input Enable (0x20) */ @@ -369,8 +373,9 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){ /* Set: INAUX1 Select (0x34) */ outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - /* Set: GPIO 3 + 3 Pull Up (0x18) */ - outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); + /* Set: GPIO 3 + 3 Pull Up (0x18) */ + outl(GPIOL_3_SET | GPIOL_4_SET, + gpio_addr + GPIOL_PULLUP_ENABLE); /* enable COM2 */ /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ @@ -378,48 +383,44 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){ msr.hi = 0; wrmsr(MDD_UART2_CONF, msr); - } - else{ + } else { /* Reset and disable COM2 */ msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; // reset + msr.lo = 1; // reset wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; // disabled wrmsr(MDD_UART2_CONF, msr); /* Disable the IRQ */ msr = rdmsr(MDD_LEG_IO); msr.lo |= ~(0xF << 20); - wrmsr(MDD_LEG_IO,msr); + wrmsr(MDD_LEG_IO, msr); } } - - #define HCCPARAMS 0x08 #define IPREG04 0xA0 #define USB_HCCPW_SET (1 << 1) #define UOCCAP 0x00 #define APU_SET (1 << 15) #define UOCMUX 0x04 - #define PMUX_HOST 0x02 - #define PMUX_DEVICE 0x03 +#define PMUX_HOST 0x02 +#define PMUX_DEVICE 0x03 #define PUEN_SET (1 << 2) #define UDCDEVCTL 0x404 #define UDC_SD_SET (1 << 10) #define UOCCTL 0x0C #define PADEN_SET (1 << 7) - static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint32_t * bar; + uint32_t *bar; msr_t msr; device_t dev; - - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); - if(dev){ + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); + if (dev) { /* Serial Short Detect Enable */ msr = rdmsr(USB2_SB_GLD_MSR_CONF); @@ -427,7 +428,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) wrmsr(USB2_SB_GLD_MSR_CONF, msr); /* write to clear diag register */ - wrmsr(USB2_SB_GLD_MSR_DIAG,rdmsr(USB2_SB_GLD_MSR_DIAG)); + wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -438,9 +439,9 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) *(bar + HCCPARAMS) = 0x00005012; } - - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if(dev){ + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_OTG, 0); + if (dev) { bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); *(bar + UOCMUX) &= PUEN_SET; @@ -448,8 +449,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /* Host or Device? */ if (sb->enable_USBP4_device) { *(bar + UOCMUX) |= PMUX_DEVICE; - } - else{ + } else { *(bar + UOCMUX) |= PMUX_HOST; } @@ -460,35 +460,41 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) } /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device, - * then perform the following sequence: + * then perform the following sequence: * * - set SD bit in DEVCTRL udc register * - set PADEN (former OTGPADEN) bit in uoc register * - set APU bit in uoc register */ if (sb->enable_USBP4_device) { - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if(dev){ - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_UDC, 0); + if (dev) { + bar = (uint32_t *) pci_read_config32(dev, + PCI_BASE_ADDRESS_0); *(bar + UDCDEVCTL) |= UDC_SD_SET; } - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if(dev){ - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_OTG, 0); + if (dev) { + bar = (uint32_t *) pci_read_config32(dev, + PCI_BASE_ADDRESS_0); *(bar + UOCCTL) |= PADEN_SET; *(bar + UOCCAP) |= APU_SET; } } /* Disable virtual PCI UDC and OTG headers */ - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if(dev){ + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_UDC, 0); + if (dev) { pci_write_config8(dev, 0x7C, 0xDEADBEEF); } - dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if(dev){ + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_OTG, 0); + if (dev) { pci_write_config8(dev, 0x7C, 0xDEADBEEF); } } @@ -499,20 +505,22 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /* Called from northbridge init (Pre-VSA). */ /* **/ /* ***************************************************************************/ -void chipsetinit (void){ +void chipsetinit(void) +{ device_t dev; msr_t msr; uint32_t msrnum; - struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + struct southbridge_amd_cs5536_config *sb = + (struct southbridge_amd_cs5536_config *)dev->chip_info; struct msrinit *csi; - outb( P80_CHIPSET_INIT, 0x80); + outb(P80_CHIPSET_INIT, 0x80); /* we hope NEVER to be in linuxbios when S3 resumes - if (! IsS3Resume()) */ + if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table; - for(; aci->ioreg; aci++) { + for (; aci->ioreg; aci++) { outl(aci->regdata, aci->ioreg); inl(aci->ioreg); } @@ -520,43 +528,42 @@ void chipsetinit (void){ pmChipsetInit(); } - /* set hd IRQ */ - outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); + outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - /* Allow IO read and writes during a ATA DMA operation.*/ - /* This could be done in the HD rom but do it here for easier debugging.*/ + /* Allow IO read and writes during a ATA DMA operation. */ + /* This could be done in the HD rom but do it here for easier debugging. */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; wrmsr(msrnum, msr); - /* Enable Post Primary IDE.*/ + /* Enable Post Primary IDE. */ msrnum = GLPCI_SB_CTRL; msr = rdmsr(msrnum); - msr.lo |= GLPCI_CRTL_PPIDE_SET; + msr.lo |= GLPCI_CRTL_PPIDE_SET; wrmsr(msrnum, msr); - csi = SB_MASTER_CONF_TABLE; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++) { msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; - wrmsr(csi->msrnum, msr); // MSR - see table above + wrmsr(csi->msrnum, msr); // MSR - see table above } - /* Flash BAR size Setup*/ - printk_err("%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); + /* Flash BAR size Setup */ + printk_err("%sDoing ChipsetFlashSetup()\n", + sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup(); /* */ - /* Set up Hardware Clock Gating*/ + /* Set up Hardware Clock Gating */ /* */ { csi = CS5536_CLOCK_GATING_TABLE; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++) { msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; wrmsr(csi->msrnum, msr); // MSR - see table above @@ -566,7 +573,8 @@ void chipsetinit (void){ static void southbridge_init(struct device *dev) { - struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + struct southbridge_amd_cs5536_config *sb = + (struct southbridge_amd_cs5536_config *)dev->chip_info; int i; /* * struct device *gpiodev; @@ -578,12 +586,15 @@ static void southbridge_init(struct device *dev) lpc_init(sb); uarts_init(sb); - if (sb->enable_gpio_int_route){ - vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB, (sb->enable_gpio_int_route & 0xFFFF)); - vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD, (sb->enable_gpio_int_route >> 16)); + if (sb->enable_gpio_int_route) { + vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB, + (sb->enable_gpio_int_route & 0xFFFF)); + vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD, + (sb->enable_gpio_int_route >> 16)); } - printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash); + printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, + sb->enable_ide_nand_flash); if (sb->enable_ide_nand_flash == 1) { enable_ide_nand_flash_header(); } @@ -592,13 +603,13 @@ static void southbridge_init(struct device *dev) /* disable unwanted virtual PCI devices */ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { - printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]); + printk_debug("Disabling VPCI device: 0x%08X\n", + sb->unwanted_vpci[i]); outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); - outl(0xDEADBEEF, 0xCFC); + outl(0xDEADBEEF, 0xCFC); } } - static void southbridge_enable(struct device *dev) { printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev); @@ -613,24 +624,24 @@ static void cs5536_pci_dev_enable_resources(device_t dev) } static struct device_operations southbridge_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = cs5536_pci_dev_enable_resources, - .init = southbridge_init, -// .enable = southbridge_enable, - .scan_bus = scan_static_bus, + .init = southbridge_init, +// .enable = southbridge_enable, + .scan_bus = scan_static_bus, }; static struct pci_driver cs5536_pci_driver __pci_driver = { - .ops = &southbridge_ops, + .ops = &southbridge_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_ISA }; struct chip_operations southbridge_amd_cs5536_ops = { CHIP_NAME("AMD Geode CS5536 Southbridge") - /* This is only called when this device is listed in the - * static device tree. - */ - .enable_dev = southbridge_enable, + /* This is only called when this device is listed in the + * static device tree. + */ + .enable_dev = southbridge_enable, }; |