diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-17 22:09:26 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-17 22:09:26 +0000 |
| commit | 78b40335841eae958865f67ac8ee0020fd43aead (patch) | |
| tree | ee316429e66c4236ca9b214605413e3a32df8433 /src/southbridge/amd/cs5536/cs5536.c | |
| parent | 527aedc17bbbc65f665c4d925a72b3e120d9d7ec (diff) | |
| download | coreboot-78b40335841eae958865f67ac8ee0020fd43aead.tar.xz | |
more warnings gone...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/cs5536.c')
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 905d71f052..e974d399d1 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -35,7 +35,7 @@ #include "cs5536.h" struct msrinit { - uint32_t msrnum; + u32 msrnum; msr_t msr; }; @@ -61,8 +61,8 @@ struct msrinit CS5536_CLOCK_GATING_TABLE[] = { }; struct acpiinit { - uint16_t ioreg; - uint32_t regdata; + u16 ioreg; + u32 regdata; }; struct acpiinit acpi_init_table[] = { @@ -95,7 +95,7 @@ struct FLASH_DEVICE FlashInitTable[] = { #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -uint32_t FlashPort[] = { +u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, @@ -111,8 +111,8 @@ uint32_t FlashPort[] = { /* ***************************************************************************/ static void pmChipsetInit(void) { - uint32_t val = 0; - uint16_t port; + u32 val = 0; + u16 port; port = (PMS_IO_BASE + 0x010); val = 0x0E00; /* 1ms */ @@ -427,7 +427,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint8_t *bar; + u32 bar; msr_t msr; device_t dev; @@ -443,7 +443,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /* write to clear diag register */ wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); - bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Make HCCPARAMS writeable */ write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET); @@ -455,7 +455,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET); @@ -483,8 +483,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UDCDEVCTL, read32(bar + UDCDEVCTL) | UDC_SD_SET); @@ -493,8 +492,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET); write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET); } @@ -524,7 +522,7 @@ void chipsetinit(void) { device_t dev; msr_t msr; - uint32_t msrnum; + u32 msrnum; struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; struct msrinit *csi; |