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| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2012-07-20 10:21:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-24 12:18:28 +0200 |
| commit | b5dfcae09728d38d8049e348a2b7654087b3a734 (patch) | |
| tree | 67bbf317e5dd625989e2677bccc88a12134f9a63 /src/southbridge/amd/cs5536/cs5536.c | |
| parent | fa418e3c66ca1728f41bd5811a77dcb14253441c (diff) | |
| download | coreboot-b5dfcae09728d38d8049e348a2b7654087b3a734.tar.xz | |
cs5536: add smbus support in ramstage
With this patch it is possible to use the smbus in ramstage. The
biggest part of the patch is a simple code split into a general
part (smbus.h) and the concrete users (early_smbus.c and cs5536.c).
After the switch from romstage to ramstage the smb base address
has changed, but that is no problem as the new base address is
stored in bar0 of the ISA bridge. It could also be read via msr,
but via PCI it is simpler. I used the following patch as
reference on how to readout the new base address:
http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html
Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1243
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/cs5536/cs5536.c')
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 872de36887..0c0368f217 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> +#include <device/smbus.h> #include <console/console.h> #include <stdint.h> #include <pc80/isa-dma.h> @@ -33,6 +34,7 @@ #include <stdlib.h> #include "chip.h" #include "cs5536.h" +#include "smbus.h" struct msrinit { u32 msrnum; @@ -667,6 +669,23 @@ static void southbridge_enable(struct device *dev) } +static int lsmbus_read_byte(device_t dev, u8 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x10); + + return do_smbus_read_byte(res->base, device, address); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = lsmbus_read_byte, +}; + static struct device_operations southbridge_ops = { .read_resources = cs5536_read_resources, .set_resources = pci_dev_set_resources, @@ -674,6 +693,7 @@ static struct device_operations southbridge_ops = { .init = southbridge_init, // .enable = southbridge_enable, .scan_bus = scan_static_bus, + .ops_smbus_bus = &lops_smbus_bus, }; static const struct pci_driver cs5536_pci_driver __pci_driver = { |