diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-02-03 13:49:24 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-03 13:49:24 +0000 |
| commit | 5a559d4386b4f659bfeddffa8f38670e24a35ac0 (patch) | |
| tree | 2ba497b765b18431b6018af28fc80df360fe71f7 /src/southbridge/amd/cs5536/cs5536.c | |
| parent | fa742da56be11090fc713c21bc3faf786d99b135 (diff) | |
| download | coreboot-5a559d4386b4f659bfeddffa8f38670e24a35ac0.tar.xz | |
The UART2 on the AMD cs5536 is incorrectly configured in two places.
GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault).
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Edwin Beasant <edwin_beasant@virtensys.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/cs5536.c')
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 89e0cf5951..474424bba6 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -298,7 +298,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - /* GPIO8 - UART1_RX */ + /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ @@ -356,18 +356,18 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) msr.lo |= sb->com2_irq << 28; wrmsr(MDD_IRQM_YHIGH, msr); - /* GPIO4 - UART2_RX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - - /* GPIO3 - UART2_TX */ + /* GPIO3 - UART2_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); + /* GPIO4 - UART2_TX */ + /* Set: Output Enable (0x4) */ + outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); + /* Set: OUTAUX1 Select (0x10) */ + outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); + /* Set: GPIO 3 and 4 Pull Up (0x18) */ outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); |