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authorMyles Watson <mylesgw@gmail.com>2009-02-12 21:30:06 +0000
committerMyles Watson <mylesgw@gmail.com>2009-02-12 21:30:06 +0000
commit552b327ca39f12b21a9e1a8dfdb71f3f26abf256 (patch)
tree6b47a55381e7cbe3c58afec9db4612d32fc5dfd3 /src/southbridge/amd/cs5536
parent7f86ed122068f34de4e8723b83e0d9b053cea9a2 (diff)
downloadcoreboot-552b327ca39f12b21a9e1a8dfdb71f3f26abf256.tar.xz
This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536')
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c8
-rw-r--r--src/southbridge/amd/cs5536/cs5536_ide.c4
2 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 0acc5ca5c2..e9dc868df1 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -579,7 +579,7 @@ static void southbridge_init(struct device *dev)
* unsigned short gpiobase = MDD_GPIO;
*/
- printk_err("cs5536: %s\n", __FUNCTION__);
+ printk_err("cs5536: %s\n", __func__);
setup_i8259();
lpc_init(sb);
uarts_init(sb);
@@ -591,7 +591,7 @@ static void southbridge_init(struct device *dev)
(sb->enable_gpio_int_route >> 16));
}
- printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__,
+ printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __func__,
sb->enable_ide_nand_flash);
if (sb->enable_ide_nand_flash == 1) {
enable_ide_nand_flash_header();
@@ -610,13 +610,13 @@ static void southbridge_init(struct device *dev)
static void southbridge_enable(struct device *dev)
{
- printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev);
+ printk_err("cs5536: %s: dev is %p\n", __func__, dev);
}
static void cs5536_pci_dev_enable_resources(device_t dev)
{
- printk_err("cs5536: %s()\n", __FUNCTION__);
+ printk_err("cs5536: %s()\n", __func__);
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/cs5536_ide.c
index b0d711c948..bbb6bb5bcd 100644
--- a/src/southbridge/amd/cs5536/cs5536_ide.c
+++ b/src/southbridge/amd/cs5536/cs5536_ide.c
@@ -36,7 +36,7 @@ static void ide_init(struct device *dev)
{
uint32_t ide_cfg;
- printk_spew("cs5536_ide: %s\n", __FUNCTION__);
+ printk_spew("cs5536_ide: %s\n", __func__);
/* GPIO and IRQ setup are handled in the main chipset code. */
// Enable the channel and Post Write Buffer
@@ -49,7 +49,7 @@ static void ide_init(struct device *dev)
static void ide_enable(struct device *dev)
{
- printk_spew("cs5536_ide: %s\n", __FUNCTION__);
+ printk_spew("cs5536_ide: %s\n", __func__);
}