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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 21:20:04 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:29:13 +0200
commit1bcd7fcb6199528fc82685e161d6b39f273a1962 (patch)
tree90e07ca28aa8514375b27b9c638a33701f921d52 /src/southbridge/amd/cs5536
parent15279a9696c70b82c2223264a505da9122f9aa7b (diff)
downloadcoreboot-1bcd7fcb6199528fc82685e161d6b39f273a1962.tar.xz
src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Diffstat (limited to 'src/southbridge/amd/cs5536')
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 4651257056..345752e044 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -560,7 +560,7 @@ void chipsetinit(void)
outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
/* Allow IO read and writes during a ATA DMA operation. */
- /* This could be done in the HD rom but do it here for easier debugging. */
+ /* This could be done in the HD ROM but do it here for easier debugging. */
msrnum = ATA_SB_GLD_MSR_ERR;
msr = rdmsr(msrnum);
msr.lo &= ~0x100;