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authorMartin Roth <martin.roth@se-eng.com>2014-12-16 20:53:49 -0700
committerMartin Roth <gaumless@gmail.com>2014-12-17 16:55:44 +0100
commit55e31a9e335943ef26d182ade53103df367e8745 (patch)
tree1505b4bccfc7c1f93d8f5a96420c88cf0ed06a9a /src/southbridge/amd/cs5536
parentdcf253c74e3eb88e738f425c9a9bfd897736c2b0 (diff)
downloadcoreboot-55e31a9e335943ef26d182ade53103df367e8745.tar.xz
southbridge/amd amd81XX, cs553X & sr5650 spelling fixes
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7842 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/amd/cs5536')
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 1f7eab87ad..3d873d0d8f 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -447,7 +447,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- /* Make HCCPARAMS writeable */
+ /* Make HCCPARAMS writable */
write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
/* ; EECP=50h, IST=01h, ASPC=1 */