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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-22 01:15:22 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-04 21:21:42 +0000
commit33ff44c37ccb96c209b002e5430deefc00cc5591 (patch)
tree48442d78b1aa677d1489bfeb776ee850f2497a65 /src/southbridge/amd/pi
parent153ff207ad8e58c3753a0dfb4941618345646706 (diff)
downloadcoreboot-33ff44c37ccb96c209b002e5430deefc00cc5591.tar.xz
binaryPI: Use pcidev_on_root()
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: If536adf11aacef8faa3455692285552f97531df9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/pi')
-rw-r--r--src/southbridge/amd/pi/hudson/lpc.c2
-rw-r--r--src/southbridge/amd/pi/hudson/sd.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index 587fd95b27..9b8753a3fe 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -38,7 +38,7 @@ static void lpc_init(struct device *dev)
struct device *sm_dev;
/* Enable the LPC Controller */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ sm_dev = pcidev_on_root(0x14, 0);
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);
diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c
index a87367fef5..8bb7538b29 100644
--- a/src/southbridge/amd/pi/hudson/sd.c
+++ b/src/southbridge/amd/pi/hudson/sd.c
@@ -25,7 +25,7 @@ static void sd_init(struct device *dev)
{
u32 stepping;
- stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
+ stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
struct southbridge_amd_pi_hudson_config *sd_chip =
(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);