diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-10-01 10:59:56 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-26 06:53:28 +0000 |
| commit | 8ccc8fdf26a9172ef8023e91630bdf88239170c7 (patch) | |
| tree | 2e5d2057da51c3037e9772410c4497b532150531 /src/southbridge/amd/pi | |
| parent | 0141f0d6b899d0f177cce5820a5fc7c6dad0c13d (diff) | |
| download | coreboot-8ccc8fdf26a9172ef8023e91630bdf88239170c7.tar.xz | |
sb/amd/*/*/pci_devs.h: Reduce the difference
Also add missing <device/pci_def.h>
Change-Id: I227f0c2a4ccb486f1d5560e3f64bc6208a456d68
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/southbridge/amd/pi')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/pci_devs.h | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 7c29380e18..5dece330f9 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -3,18 +3,20 @@ #ifndef _PI_HUDSON_PCI_DEVS_H_ #define _PI_HUDSON_PCI_DEVS_H_ +#include <device/pci_def.h> + #define BUS0 0 /* XHCI */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 #define XHCI_DEVID 0x7814 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define XHCI2_DEV 0x10 #define XHCI2_FUNC 1 #define XHCI2_DEVID 0x7814 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) /* SATA */ #define SATA_DEV 0x11 @@ -22,7 +24,7 @@ #define SATA_IDE_DEVID 0x7800 #define AHCI_DEVID_MS 0x7801 #define AHCI_DEVID_AMD 0x7804 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* OHCI */ #define OHCI1_DEV 0x12 @@ -34,10 +36,10 @@ #define OHCI4_DEV 0x14 #define OHCI4_FUNC 5 #define OHCI_DEVID 0x7807 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) /* EHCI */ #define EHCI1_DEV 0x12 @@ -47,48 +49,48 @@ #define EHCI3_DEV 0x16 #define EHCI3_FUNC 2 #define EHCI_DEVID 0x7808 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 #define SMBUS_DEVID 0x780B -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) /* IDE */ #if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) #define IDE_DEV 0x14 #define IDE_FUNC 1 #define IDE_DEVID 0x780C -#define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) #endif /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 #define HDA_DEVID 0x780D -#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) /* LPC BUS */ #define PCU_DEV 0x14 #define LPC_DEV PCU_DEV #define LPC_FUNC 3 #define LPC_DEVID 0x780E -#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) /* PCI Ports */ #define SB_PCI_PORT_DEV 0x14 #define SB_PCI_PORT_FUNC 4 #define SB_PCI_PORT_DEVID 0x780F -#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) /* SD Controller */ #define SD_DEV 0x14 #define SD_FUNC 7 #define SD_DEVID 0x7806 -#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) /* PCIe Ports */ #if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) @@ -101,10 +103,10 @@ #define SB_PCIE_PORT2_DEVID 0x7821 #define SB_PCIE_PORT3_DEVID 0x7822 #define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif #endif /* _PI_HUDSON_PCI_DEVS_H_ */ |