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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-09 08:08:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-21 11:37:15 +0000
commit282717e5cc325595143d96036653b03ac0fcf480 (patch)
tree5971d5fafa16db7306b7f357c5377f522a6a7b05 /src/southbridge/amd/pi
parentb915faedd503f7904fef9f7ff531262981061473 (diff)
downloadcoreboot-282717e5cc325595143d96036653b03ac0fcf480.tar.xz
sb/amd/{agesa,pi,cimx}/bootblock: Use simple PCI config accessor
Change-Id: I5e1f2ceda37927d7a75660affee8504f9f8aff15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37597 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/pi')
-rw-r--r--src/southbridge/amd/pi/hudson/bootblock.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index 77a4570830..6b7595fc0e 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -36,15 +36,15 @@ static void hudson_enable_rom(void)
dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
- reg8 = pci_io_read_config8(dev, 0x48);
+ reg8 = pci_s_read_config8(dev, 0x48);
reg8 |= (1 << 3) | (1 << 4);
- pci_io_write_config8(dev, 0x48, reg8);
+ pci_s_write_config8(dev, 0x48, reg8);
/* LPC ROM address range 1: */
/* Enable LPC ROM range mirroring start at 0x000e(0000). */
- pci_io_write_config16(dev, 0x68, 0x000e);
+ pci_s_write_config16(dev, 0x68, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
- pci_io_write_config16(dev, 0x6a, 0x000f);
+ pci_s_write_config16(dev, 0x6a, 0x000f);
/* LPC ROM address range 2: */
/*
@@ -54,9 +54,9 @@ static void hudson_enable_rom(void)
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
- pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+ pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
- pci_io_write_config16(dev, 0x6e, 0xffff);
+ pci_s_write_config16(dev, 0x6e, 0xffff);
}
void bootblock_early_southbridge_init(void)