diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/amd/pi | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
| download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/amd/pi')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/early_setup.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.h | 8 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 679f233f02..1b5326b88e 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -46,7 +46,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ +#define PIRQ_SD 0x17 /* SD */ #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index d95385be1e..b5a86dc959 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -163,7 +163,7 @@ static void enable_wideio(uint8_t port, uint16_t size) tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp |= alt_wideio_enable[port]; pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); - } else { /* 512 */ + } else { /* 512 */ tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp &= ~alt_wideio_enable[port]; pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 091464f14d..922c608a67 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -121,7 +121,7 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 -#define SPI_CNTRL0 0x00 +#define SPI_CNTRL0 0x00 #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) /* Nominal is 16.7MHz on older devices, 33MHz on newer */ #define SPI_READ_MODE_NOM 0x00000000 @@ -137,7 +137,7 @@ #define SPI_CNTRL1 0x0c /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ -#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) +#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) #define SPI_NORM_SPEED_SH 12 #define SPI_FAST_SPEED_SH 8 @@ -153,10 +153,10 @@ #define SPI_SPEED_800K (BIT(2) | BIT(0)) #define SPI_NORM_SPEED_NEW_SH 12 #define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_ALT_SPEED_NEW_SH 4 #define SPI_TPM_SPEED_NEW_SH 0 -#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) static inline int hudson_sata_enable(void) |