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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-07-20 08:24:49 +0300
committerAnton Kochkov <anton.kochkov@gmail.com>2012-08-02 12:54:55 +0200
commitf803ac4a4550b6f767b67117731446d75db85a68 (patch)
tree5d4f9b4b6b0d2e2479573dfe8d30f78699936abc /src/southbridge/amd/rs690/cmn.c
parentbbf249649336801517f77d1f76aafeaf20d96180 (diff)
downloadcoreboot-f803ac4a4550b6f767b67117731446d75db85a68.tar.xz
AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base
The code in rs690 or rs780 is always used with K8 or AMDFAM10 northbridge. Without GFXUMA, both of these set the same static value indirectly using the variable uma_memory_base. Make the register setting with immediate value, to remove the obscure use of variable uma_memory_base. Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1246 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Diffstat (limited to 'src/southbridge/amd/rs690/cmn.c')
-rw-r--r--src/southbridge/amd/rs690/cmn.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 68c46e9728..004cf78898 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -316,7 +316,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
void rs690_set_tom(device_t nb_dev)
{
/* set TOM */
+#if CONFIG_GFXUMA
pci_write_config32(nb_dev, 0x90, uma_memory_base);
nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
+#else
+ /* 1GB system memory supposed */
+ pci_write_config32(nb_dev, 0x90, 0x38000000);
+ nbmc_write_index(nb_dev, 0x1e, 0x38000000);
+#endif
}