diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-31 19:22:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:22:46 +0200 |
| commit | ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch) | |
| tree | 9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/amd/rs690/gfx.c | |
| parent | 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff) | |
| download | coreboot-ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1.tar.xz | |
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/rs690/gfx.c')
| -rw-r--r-- | src/southbridge/amd/rs690/gfx.c | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c index 57d6628303..bcba43524a 100644 --- a/src/southbridge/amd/rs690/gfx.c +++ b/src/southbridge/amd/rs690/gfx.c @@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* done by enable_pci_bar3() before */ /* step 6 SBIOS compile flags */ - if (cfg->gfx_tmds) { - /* step 6.2.2 Clock-Muxing Control */ - /* step 6.2.2.1 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16); + if (cfg->gfx_tmds) { + /* step 6.2.2 Clock-Muxing Control */ + /* step 6.2.2.1 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16); - /* step 6.2.2.2 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10); + /* step 6.2.2.2 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10); - /* step 6.2.2.3 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26); + /* step 6.2.2.3 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26); - /* step 6.2.3 Lane-Muxing Control */ - /* step 6.2.3.1 */ - set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8); + /* step 6.2.3 Lane-Muxing Control */ + /* step 6.2.3.1 */ + set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8); - /* step 6.2.4 Received Data Control */ - /* step 6.2.4.1 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16); + /* step 6.2.4 Received Data Control */ + /* step 6.2.4.1 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16); - /* step 6.2.4.2 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18); + /* step 6.2.4.2 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18); - /* step 6.2.4.3 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20); + /* step 6.2.4.3 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20); - /* step 6.2.4.4 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22); + /* step 6.2.4.4 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22); - /* step 6.2.5 PLL Power Down Control */ - /* step 6.2.5.1 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6); + /* step 6.2.5 PLL Power Down Control */ + /* step 6.2.5.1 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6); - /* step 6.2.6 Driving Strength Control */ - /* step 6.2.6.1 */ - set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24); + /* step 6.2.6 Driving Strength Control */ + /* step 6.2.6.1 */ + set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24); - /* step 6.2.6.2 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); - } + /* step 6.2.6.2 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); + } - printk(BIOS_INFO, "rs690_gfx_init step6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step6.\n"); /* step 7 compliance state, (only need if CMOS option is enabled) */ /* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */ |