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| author | Stefan Reinauer <reinauer@chromium.org> | 2011-10-31 12:56:45 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-01 19:07:45 +0100 |
| commit | 5ff7c13e858a31addf1558731a12cf6c753b576d (patch) | |
| tree | 82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src/southbridge/amd/rs690/ht.c | |
| parent | 784544b934d67dc85ccfcf33e04ff148045836ad (diff) | |
| download | coreboot-5ff7c13e858a31addf1558731a12cf6c753b576d.tar.xz | |
remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/rs690/ht.c')
| -rw-r--r-- | src/southbridge/amd/rs690/ht.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index dba28e789a..5d816e59f4 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -28,25 +28,25 @@ static void ht_dev_set_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT == 1 - unsigned reg; + unsigned reg; device_t k8_f1; resource_t rbase, rend; u32 base, limit; struct resource *resource; - + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); - + resource = probe_resource(dev, 0x1C); if (resource) { - set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ - set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses pci_write_config32(dev, 0x1C, resource->base); /* Enable MMCONFIG decoding. */ set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register. */ set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 - + // setup resource nonposted in k8 mmio /* Get the base address */ rbase = resource->base; @@ -74,9 +74,9 @@ static void ht_dev_set_resources(device_t dev) limit &= 0x00000048; limit |= ((rend >> 8) & 0xffffff00); limit |= (sblk << 4); - limit |= (1 << 7); + limit |= (1 << 7); printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit); - pci_write_config32(k8_f1, reg+4, limit); + pci_write_config32(k8_f1, reg+4, limit); pci_write_config32(k8_f1, reg, base); } } @@ -88,13 +88,13 @@ static void ht_dev_read_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT == 1 struct resource *res; - - printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); - set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 #endif pci_dev_read_resources(dev); - + #if CONFIG_EXT_CONF_SUPPORT == 1 /* Add an MMCONFIG resource. */ res = new_resource(dev, 0x1C); @@ -104,9 +104,9 @@ static void ht_dev_read_resources(device_t dev) res->gran = log2(res->size); res->limit = 0xffffffffffffffffULL; /* 64bit */ res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED; - + compact_resources(dev); -#endif +#endif } /* for UMA internal graphics */ |