Patch for AMD RS690 chipset.

All the PCIe slots are enabled in this patch except power management.

Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 228 insertions, 0 deletions

diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c
new file mode 100644
index 0000000000..dab5167d94
--- /dev/null
+++ b/src/southbridge/amd/rs690/rs690.c
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include "rs690.h"
+
+static device_t find_nb_dev(device_t dev, u32 devfn)
+{
+	device_t nb_dev;
+
+	nb_dev = dev_find_slot(dev->bus->secondary, devfn);
+
+	if (!nb_dev)
+		return nb_dev;
+
+	if ((nb_dev->vendor != PCI_VENDOR_ID_ATI)
+	    || (nb_dev->device != PCI_DEVICE_ID_ATI_RS690_HT)) {
+		u32 id;
+		id = pci_read_config32(nb_dev, PCI_VENDOR_ID);
+		if (id != (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_RS690_HT << 16))) {
+			nb_dev = 0;
+		}
+	}
+	return nb_dev;
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_MiscClockCtrl
+*****************************************/
+void static rs690_config_misc_clk(device_t nb_dev)
+{
+	u32 reg;
+	u16 word;
+	/* u8 byte; */
+	struct bus pbus; /* fake bus for dev0 fun1 */
+
+	reg = pci_read_config32(nb_dev, 0x4c);
+	reg |= 1 << 0;
+	pci_write_config32(nb_dev, 0x4c, reg);
+
+	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
+	word &= 0xf00;
+	 pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+
+	word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
+	word &= ~((1 << 12) | (1 << 13) | (1 << 14));
+	word |= 1 << 13;
+	pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
+
+	reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+	reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
+	pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+
+	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+	reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
+	reg |= 1 << 13;
+	pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+
+	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg |= 1 << 24;
+	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+
+	reg = nbmc_read_index(nb_dev, 0x7a);
+	reg &= ~0x3f;
+	reg |= 1 << 2;
+	reg &= ~(1 << 6);
+	set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
+	nbmc_write_index(nb_dev, 0x7a, reg);
+	/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
+	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg &= ~(1 << 23);
+	reg |= 1 << 24;
+	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+#if 0
+	/* Powerdown reference clock to graphics core PLL in northbridge only mode */
+	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+	reg |= 1 << 21;
+	pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+
+	/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
+	reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+	reg |= (1 << 23) | (1 << 24);
+	pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+
+	/* Powerdown clock to memory controller in northbridge only mode */
+	byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
+	byte |= 1 << 0;
+	pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
+
+	/* CLKCFG:0xE8 Bit[17] = 0x1 	 Powerdown clock to IOC GFX block in no external graphics mode */
+	/* TODO: */
+#endif
+
+	reg = pci_read_config32(nb_dev, 0x4c);
+	reg &= ~(1 << 0);
+	pci_write_config32(nb_dev, 0x4c, reg);
+
+	set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
+}
+
+/***********************************************
+*	0:00.0  NBCFG	:
+*	0:00.1  CLK	: bit 0 of nb_cfg 0x4c : 0 - disable, default
+*	0:01.0  P2P Internal:
+*	0:02.0  P2P	: bit 2 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
+*	0:03.0  P2P	: bit 3 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
+*	0:04.0  P2P	: bit 4 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
+*	0:05.0  P2P	: bit 5 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
+*	0:06.0  P2P	: bit 6 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
+*	0:07.0  P2P	: bit 7 of nbmiscind 0x0c : 0 - enable, default	   + 32 * 2
+*	0:08.0  NB2SB	: bit 6 of nbmiscind 0x00 : 0 - disable, default   + 32 * 1
+* case 0 will be called twice, one is by cpu in hypertransport.c line458,
+* the other is by rs690.
+***********************************************/
+void rs690_enable(device_t dev)
+{
+	device_t nb_dev = 0, sb_dev = 0;
+	int index = -1;
+	u32 i;
+	u32 devfn;
+	u32 deviceid, vendorid;
+
+	vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
+	deviceid = (vendorid >> 16) & 0xffff;
+	vendorid &= 0xffff;
+	printk_info("rs690_enable VID=0x%x, DID=0x%x\n", vendorid, deviceid);
+
+	/**********************************************************
+	* Work for bus0, internal GFX located on bus1 and will return after find_nb_dev.
+	**********************************************************/
+	i = (dev->path.u.pci.devfn) & ~7;
+	for (devfn = 0; devfn <= i; devfn += (1 << 3)) {
+		nb_dev = find_nb_dev(dev, devfn);
+		if (nb_dev)
+			break;
+	}
+	if (!nb_dev) {
+		printk_info("CAN NOT FIND RS690 DEVICE!\n");
+		return;		/* nb_dev is not dev */
+	}
+
+	/* sb_dev (dev 8) is a bridge that links to southbridge. */
+	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	if (!sb_dev) {
+		printk_info("rs690_enable CAN NOT FIND SB bridge, HALT!\n");
+		for (;;) ;
+	}
+
+	printk_info("rs690_enable bus0, dev=0x%x\n", (dev->path.u.pci.devfn - devfn) >> 3);
+	switch (dev->path.u.pci.devfn - devfn) {
+	case 0:		/* bus0, dev0, fun0; */
+		printk_info("Bus-0, Dev-0, Fun-0.\n");
+		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
+		config_gpp_core(nb_dev, sb_dev);
+		rs690_gpp_sb_init(nb_dev, sb_dev, 8);
+		/* set SB payload size: 64byte */
+		set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11);
+
+		/* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */
+		rs690_config_misc_clk(nb_dev);
+		break;
+
+	case 1 << 3:		/* bus0, dev1 */
+		printk_info("Bus-0, Dev-1, Fun-0.\n");
+		break;
+	case 2 << 3:		/* bus0, dev2,3, two GFX */
+	case 3 << 3:
+		printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
+		index = (dev->path.u.pci.devfn - devfn) >> 3;
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
+				       (dev->enabled ? 0 : 1) << index);
+		if (dev->enabled)
+			rs690_gfx_init(nb_dev, dev, index);
+		break;
+	case 4 << 3:		/* bus0, dev4-7, four GPP */
+	case 5 << 3:
+	case 6 << 3:
+	case 7 << 3:
+		printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
+			    dev->enabled);
+		index = (dev->path.u.pci.devfn - devfn) >> 3;
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << index,
+				       (dev->enabled ? 0 : 1) << index);
+		if (dev->enabled)
+			rs690_gpp_sb_init(nb_dev, dev, index);
+		break;
+	case 8 << 3:		/* bus0, dev8, SB */
+		printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
+		set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
+				       (dev->enabled ? 1 : 0) << 6);
+		if (dev->enabled)
+			rs690_gpp_sb_init(nb_dev, dev, index);
+		disable_pcie_bar3(nb_dev);
+		break;
+	default:
+		printk_debug("unknown dev: %s\n", dev_path(dev));
+	}
+}
+
+struct chip_operations southbridge_amd_rs690_ops = {
+	CHIP_NAME("ATI RS690")
+	.enable_dev = rs690_enable,
+};