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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-03 20:41:04 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-10-04 14:30:52 +0200 |
| commit | 18cd8a64a46b85af5bf284165ce412188fc31948 (patch) | |
| tree | 8ce52f4941cfe435fd71b01abc93bc7655560812 /src/southbridge/amd/rs690 | |
| parent | 5c22825c1924b1f5fb9cebff8e13b83792d3ecb9 (diff) | |
| download | coreboot-18cd8a64a46b85af5bf284165ce412188fc31948.tar.xz | |
src/southbridge: Remove unnecessary semicolon
Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16857
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/rs690')
| -rw-r--r-- | src/southbridge/amd/rs690/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 043c2eef5c..db65686a11 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* step 6d: ASPM L1 for the southbridge link */ /* To enable L1s in the southbridge*/ - /* step 6e: ASPM L1 for GPP link(s) */; + /* step 6e: ASPM L1 for GPP link(s) */ set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); |