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authorStefan Reinauer <stepan@coresystems.de>2009-02-28 20:10:20 +0000
committerStefan Reinauer <stepan@openbios.org>2009-02-28 20:10:20 +0000
commit2b34db8d1de2d63ffa829fe03db0ce2aaba40233 (patch)
treeba18eb28d25a5e5d28c3b8609b5a292982eed08c /src/southbridge/amd/rs690
parent3c924d2f48ba1bb6a9d5a20453f230bb6be726e0 (diff)
downloadcoreboot-2b34db8d1de2d63ffa829fe03db0ce2aaba40233.tar.xz
coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/rs690')
-rw-r--r--src/southbridge/amd/rs690/rs690.c2
-rw-r--r--src/southbridge/amd/rs690/rs690_cmn.c8
2 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c
index 3caa00e9c8..e5d6a1e2e7 100644
--- a/src/southbridge/amd/rs690/rs690.c
+++ b/src/southbridge/amd/rs690/rs690.c
@@ -144,7 +144,7 @@ void rs690_enable(device_t dev)
/* NOT REACHED */
}
- dev_ind = dev->path.u.pci.devfn >> 3;
+ dev_ind = dev->path.pci.devfn >> 3;
switch (dev_ind) {
case 0: /* bus0, dev0, fun0; */
printk_info("Bus-0, Dev-0, Fun-0.\n");
diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index 302664f3c9..7b6d8fed8f 100644
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -51,9 +51,9 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
- dev->path.u.pci.devfn);
+ dev->path.pci.devfn);
addr |= dev->bus->secondary << 20 | /* bus num */
- dev->path.u.pci.devfn << 12 | reg;
+ dev->path.pci.devfn << 12 | reg;
return *((u32 *) addr);
}
@@ -64,9 +64,9 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
- dev->path.u.pci.devfn);*/
+ dev->path.pci.devfn);*/
addr |= dev->bus->secondary << 20 | /* bus num */
- dev->path.u.pci.devfn << 12 | reg_pos;
+ dev->path.pci.devfn << 12 | reg_pos;
reg = reg_old = *((u32 *) addr);
reg &= ~mask;