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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-03-04 01:06:41 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-03-04 01:06:41 +0000 |
| commit | 51001fbd81543d738a07cd36063fe5705eeff3ad (patch) | |
| tree | f552e6a0fd71a460b0ef4f012f8ba594784c4501 /src/southbridge/amd/rs690 | |
| parent | 4b95ced365dd80eb1891f0eb7a2c79a94a7d0bfc (diff) | |
| download | coreboot-51001fbd81543d738a07cd36063fe5705eeff3ad.tar.xz | |
I just went on a bugfix frenzy and fixed all printk format warnings
triggered by the AMD 690/SB600 targets.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/rs690')
| -rw-r--r-- | src/southbridge/amd/rs690/rs690.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs690/rs690_gfx.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/rs690/rs690_pcie.c | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c index e5d6a1e2e7..40913b3388 100644 --- a/src/southbridge/amd/rs690/rs690.c +++ b/src/southbridge/amd/rs690/rs690.c @@ -129,7 +129,7 @@ void rs690_enable(device_t dev) device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c index d4c8755f8a..0ed5a81369 100644 --- a/src/southbridge/amd/rs690/rs690_gfx.c +++ b/src/southbridge/amd/rs690/rs690_gfx.c @@ -121,7 +121,7 @@ static void rs690_internal_gfx_enable(device_t dev) device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); - printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev, + printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, nb_dev); /* set APERTURE_SIZE, 128M. */ @@ -417,7 +417,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n", + printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* step 0, REFCLK_SEL, skip A11 revision */ diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c index 9691e4ed18..640fa75613 100644 --- a/src/southbridge/amd/rs690/rs690_pcie.c +++ b/src/southbridge/amd/rs690/rs690_pcie.c @@ -203,7 +203,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) device_t sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port); + printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); /* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, |