src/southbridge: Code formating

Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

3 files changed, 36 insertions, 36 deletions

diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c
index 57d6628303..bcba43524a 100644
--- a/src/southbridge/amd/rs690/gfx.c
+++ b/src/southbridge/amd/rs690/gfx.c
@@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	/* done by enable_pci_bar3() before */
 
 	/* step 6 SBIOS compile flags */
-        if (cfg->gfx_tmds) {
-                /* step 6.2.2 Clock-Muxing Control */
-                /* step 6.2.2.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+	if (cfg->gfx_tmds) {
+		/* step 6.2.2 Clock-Muxing Control */
+		/* step 6.2.2.1 */
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
 
-                /* step 6.2.2.2 */
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+		/* step 6.2.2.2 */
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
 
-                /* step 6.2.2.3 */
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+		/* step 6.2.2.3 */
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
 
-                /* step 6.2.3 Lane-Muxing Control */
-                /* step 6.2.3.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+		/* step 6.2.3 Lane-Muxing Control */
+		/* step 6.2.3.1 */
+		set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
 
-                /* step 6.2.4 Received Data Control */
-                /* step 6.2.4.1 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+		/* step 6.2.4 Received Data Control */
+		/* step 6.2.4.1 */
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
 
-                /* step 6.2.4.2 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+		/* step 6.2.4.2 */
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
 
-                /* step 6.2.4.3 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+		/* step 6.2.4.3 */
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
 
-                /* step 6.2.4.4 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+		/* step 6.2.4.4 */
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
 
-                /* step 6.2.5 PLL Power Down Control */
-                /* step 6.2.5.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+		/* step 6.2.5 PLL Power Down Control */
+		/* step 6.2.5.1 */
+		set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
 
-                /* step 6.2.6 Driving Strength Control */
-                /* step 6.2.6.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+		/* step 6.2.6 Driving Strength Control */
+		/* step 6.2.6.1 */
+		set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
 
-                /* step 6.2.6.2 */
-                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
-        }
+		/* step 6.2.6.2 */
+		set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+	}
 
-        printk(BIOS_INFO, "rs690_gfx_init step6.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step6.\n");
 
 	/* step 7 compliance state, (only need if CMOS option is enabled) */
 	/* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */
diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c
index f4bdf99097..bbb33ef648 100644
--- a/src/southbridge/amd/rs690/ht.c
+++ b/src/southbridge/amd/rs690/ht.c
@@ -52,12 +52,12 @@ static void ht_dev_set_resources(device_t dev)
 		printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend);
 		k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
 		// find a not assigned resource
-		for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
+		for ( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
 			base = pci_read_config32(k8_f1,reg);
 			limit = pci_read_config32(k8_f1,reg+4);
-			if( !(base & 3) ) break; // found a not assigned resource
+			if ( !(base & 3) ) break; // found a not assigned resource
 		}
-		if( !(base & 3) ) {
+		if ( !(base & 3) ) {
 			u32 sblk;
 			device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 			/* Remember this resource has been stored. */
@@ -90,7 +90,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
 	// we report mmconf base
 	res = probe_resource(dev, 0x1C);
-	if( res )
+	if ( res )
 		mmconf_base = res->base;
 
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c
index bcf4f4d554..043c2eef5c 100644
--- a/src/southbridge/amd/rs690/pcie.c
+++ b/src/southbridge/amd/rs690/pcie.c
@@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
 			   PCIE_GFX_COMPLIANCE))) {
 	}
 
-        if (!cfg->gfx_tmds){
+	if (!cfg->gfx_tmds){
 		/* step 3 Power Down Control for Southbridge */
 		reg = nbpcie_p_read_index(dev, 0xa2);