printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 68 insertions, 68 deletions

diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c
index 40913b3388..caf838aacf 100644
--- a/src/southbridge/amd/rs690/rs690.c
+++ b/src/southbridge/amd/rs690/rs690.c
@@ -129,7 +129,7 @@ void rs690_enable(device_t dev)
 	device_t nb_dev = 0, sb_dev = 0;
 	int dev_ind;
 
-	printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
+	printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
 
 	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
@@ -147,7 +147,7 @@ void rs690_enable(device_t dev)
 	dev_ind = dev->path.pci.devfn >> 3;
 	switch (dev_ind) {
 	case 0:		/* bus0, dev0, fun0; */
-		printk_info("Bus-0, Dev-0, Fun-0.\n");
+		printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
 		enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
 		config_gpp_core(nb_dev, sb_dev);
 		rs690_gpp_sb_init(nb_dev, sb_dev, 8);
@@ -159,11 +159,11 @@ void rs690_enable(device_t dev)
 		break;
 
 	case 1:		/* bus0, dev1 */
-		printk_info("Bus-0, Dev-1, Fun-0.\n");
+		printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
 		break;
 	case 2:		/* bus0, dev2,3, two GFX */
 	case 3:
-		printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
+		printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
 				       (dev->enabled ? 0 : 1) << dev_ind);
 		if (dev->enabled)
@@ -173,7 +173,7 @@ void rs690_enable(device_t dev)
 	case 5:
 	case 6:
 	case 7:
-		printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
+		printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
 			    dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
 				       (dev->enabled ? 0 : 1) << dev_ind);
@@ -181,7 +181,7 @@ void rs690_enable(device_t dev)
 			rs690_gpp_sb_init(nb_dev, dev, dev_ind);
 		break;
 	case 8:		/* bus0, dev8, SB */
-		printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
+		printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
 		set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
 				       (dev->enabled ? 1 : 0) << 6);
 		if (dev->enabled)
@@ -189,7 +189,7 @@ void rs690_enable(device_t dev)
 		disable_pcie_bar3(nb_dev);
 		break;
 	default:
-		printk_debug("unknown dev: %s\n", dev_path(dev));
+		printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
 	}
 }
 
diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index aa75a64f4f..026341394a 100644
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -50,7 +50,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
 {
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
-	printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+	printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.pci.devfn << 12 | reg;
@@ -63,7 +63,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
 
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
-	/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+	/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);*/
 	addr |= dev->bus->secondary << 20 |	/* bus num */
 	    dev->path.pci.devfn << 12 | reg_pos;
@@ -253,7 +253,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 		mdelay(40);
 		udelay(200);
 		lc_state = nbpcie_p_read_index(dev, 0xa5);	/* lc_state */
-		printk_debug("PcieLinkTraining port=%x:lc current state=%x\n",
+		printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
 			     port, lc_state);
 		current = lc_state & 0x3f;	/* get LC_CURRENT_STATE, bit0-5 */
 
@@ -274,7 +274,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 			reg =
 			    pci_ext_read_config32(nb_dev, dev,
 						  PCIE_VC0_RESOURCE_STATUS);
-			printk_debug("PcieTrainPort reg=0x%x\n", reg);
+			printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
 			/* check bit1 */
 			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
 				/* set bit8=1, bit0-2=bit4-6 */
diff --git a/src/southbridge/amd/rs690/rs690_early_setup.c b/src/southbridge/amd/rs690/rs690_early_setup.c
index d253f0d868..5afb7b57a3 100644
--- a/src/southbridge/amd/rs690/rs690_early_setup.c
+++ b/src/southbridge/amd/rs690/rs690_early_setup.c
@@ -133,23 +133,23 @@ static void get_cpu_rev()
 	u32 eax, ebx, ecx, edx;
 	__asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
 			  :"0"(1));
-	printk_info("get_cpu_rev EAX=0x%x.\n", eax);
+	printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
 	if (eax <= 0xfff)
-		printk_info("CPU Rev is K8_Cx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
 	else if (eax <= 0x10fff)
-		printk_info("CPU Rev is K8_Dx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
 	else if (eax <= 0x20fff)
-		printk_info("CPU Rev is K8_Ex.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
 	else if (eax <= 0x40fff)
-		printk_info("CPU Rev is K8_Fx.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
 	else if (eax == 0x60fb1 || eax == 0x60f81)	/*These two IDS are exception, they are G1. */
-		printk_info("CPU Rev is K8_G1.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
 	else if (eax <= 0X60FF0)
-		printk_info("CPU Rev is K8_G0.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
 	else if (eax <= 0x100000)
-		printk_info("CPU Rev is K8_G1.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
 	else
-		printk_info("CPU Rev is K8_10.\n");
+		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
 }
 
 static u8 get_nb_rev(device_t nb_dev)
@@ -197,19 +197,19 @@ static void rs690_htinit()
 	************************/
 	reg = pci_read_config32(k8_f0, 0x88);
 	k8_ht_freq = (reg & 0xf00) >> 8;
-	printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+	printk(BIOS_SPEW, "rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
 	rs690_f0 = PCI_DEV(0, 0, 0);
 	reg8 = pci_read_config8(rs690_f0, 0x9c);
-	printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+	printk(BIOS_SPEW, "rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
 	/* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
 	 * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
 	 */
 	if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
-		printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+		printk(BIOS_INFO, "rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
 		reg8 |= 0x1;
 		pci_write_config8(rs690_f0, 0x9c, reg8);
 	} else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
-		printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+		printk(BIOS_INFO, "rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
 		reg8 &= ~0x1;
 		pci_write_config8(rs690_f0, 0x9c, reg8);
 	}
@@ -234,7 +234,7 @@ static void k8_optimization()
 	device_t k8_f0, k8_f2, k8_f3;
 	msr_t msr;
 
-	printk_info("k8_optimization()\n");
+	printk(BIOS_INFO, "k8_optimization()\n");
 	k8_f0 = PCI_DEV(0, 0x18, 0);
 	k8_f2 = PCI_DEV(0, 0x18, 2);
 	k8_f3 = PCI_DEV(0, 0x18, 3);
@@ -425,7 +425,7 @@ static void rs690_por_htiu_index_init(device_t nb_dev)
 *****************************************/
 static void rs690_por_init(device_t nb_dev)
 {
-	printk_info("rs690_por_init\n");
+	printk(BIOS_INFO, "rs690_por_init\n");
 	/* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */
 	rs690_por_pcicfg_init(nb_dev);
 
@@ -463,19 +463,19 @@ static void rs690_before_pci_init()
 static void rs690_early_setup()
 {
 	device_t nb_dev = PCI_DEV(0, 0, 0);
-	printk_info("rs690_early_setup()\n");
+	printk(BIOS_INFO, "rs690_early_setup()\n");
 
 	/*ATINB_PrepareInit */
 	get_cpu_rev();
 	switch (get_nb_rev(nb_dev)) {	/* PCIEMiscInit */
 	case 5:
-		printk_info("NB Revision is A11.\n");
+		printk(BIOS_INFO, "NB Revision is A11.\n");
 		break;
 	case 6:
-		printk_info("NB Revision is A12.\n");
+		printk(BIOS_INFO, "NB Revision is A12.\n");
 		break;
 	case 7:
-		printk_info("NB Revision is A21.\n");
+		printk(BIOS_INFO, "NB Revision is A21.\n");
 		break;
 	}
 
diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c
index 3c87fa0447..7f76a057ac 100644
--- a/src/southbridge/amd/rs690/rs690_gfx.c
+++ b/src/southbridge/amd/rs690/rs690_gfx.c
@@ -45,7 +45,7 @@ static u32 clkind_read(device_t dev, u32 index)
 static void clkind_write(device_t dev, u32 index, u32 data)
 {
 	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
-	/* printk_info("gfx bar 2 %02x\n", gfx_bar2); */
+	/* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */
 
 	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
 	*(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
@@ -57,7 +57,7 @@ static void clkind_write(device_t dev, u32 index, u32 data)
 */
 static void rs690_gfx_read_resources(device_t dev)
 {
-	printk_info("rs690_gfx_read_resources.\n");
+	printk(BIOS_INFO, "rs690_gfx_read_resources.\n");
 
 	/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
 	   Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
@@ -77,7 +77,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	    (struct southbridge_amd_rs690_config *)dev->chip_info;
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
 	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
-	printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
 	     deviceid, vendorid);
 
 	pci_dev_init(dev);
@@ -117,12 +117,12 @@ static void rs690_internal_gfx_enable(device_t dev)
 	device_t k8_f0 = 0, k8_f2 = 0;
 	device_t nb_dev = dev_find_slot(0, 0);
 
-	printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
+	printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
 		    nb_dev);
 
 	/* set APERTURE_SIZE, 128M. */
 	l_dword = pci_read_config32(nb_dev, 0x8c);
-	printk_info("nb_dev, 0x8c=0x%x\n", l_dword);
+	printk(BIOS_INFO, "nb_dev, 0x8c=0x%x\n", l_dword);
 	l_dword &= 0xffffff8f;
 	pci_write_config32(nb_dev, 0x8c, l_dword);
 
@@ -231,13 +231,13 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
 
-	printk_info("rs690_gfx_init single_port_configuration.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n");
 
 	/* step 12 training, releases hold training for GFX port 0 (device 2) */
 	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0<<4);
 	PcieReleasePortTraining(nb_dev, dev, 2);
 	result = PcieTrainPort(nb_dev, dev, 2);
-	printk_info("rs690_gfx_init single_port_configuration step12.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step12.\n");
 
 	/* step 13 Power Down Control */
 	/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
@@ -257,7 +257,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
 
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
-		printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -274,11 +274,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
 			break;
 		}
 	}
-	printk_info("rs690_gfx_init single_port_configuration step13.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step13.\n");
 
 	/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
 	set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
-	printk_info("rs690_gfx_init single_port_configuration step14.\n");
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step14.\n");
 }
 
 /* step 15 ~ step 18 from rpr */
@@ -305,7 +305,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
 
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
-		printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -335,7 +335,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
 
 		reg32 = nbpcie_p_read_index(dev, 0xa2);
 		width = (reg32 >> 4) & 0x7;
-		printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
 		switch (width) {
 		case 1:
 		case 2:
@@ -413,13 +413,13 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
 
-	printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+	printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
 		    nb_dev, dev, port);
 
 	/* step 0, REFCLK_SEL, skip A11 revision */
 	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 9,
 			       cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9);
-	printk_info("rs690_gfx_init step0.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step0.\n");
 
 	/* step 1, lane reversal (only need if CMOS option is enabled) */
 	if (cfg->gfx_lane_reversal) {
@@ -427,13 +427,13 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 		if (cfg->gfx_dual_slot)
 			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
 	}
-	printk_info("rs690_gfx_init step1.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step1.\n");
 
 	/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
 	/* AMD calls the configuration CrossFire */
 	if (cfg->gfx_dual_slot)
 		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
-	printk_info("rs690_gfx_init step2.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step2.\n");
 
 	/* step 2, TMDS, (only need if CMOS option is enabled) */
 	if (cfg->gfx_tmds) {
@@ -461,7 +461,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 
 	/* step 4.6 bring external GFX device out of reset, wait for 1ms */
 	mdelay(1);
-	printk_info("rs690_gfx_init step4.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step4.\n");
 
 	/* step 5 program PCIE memory mapped configuration space */
 	/* done by enable_pci_bar3() before */
@@ -508,7 +508,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
                 set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
         }
 
-        printk_info("rs690_gfx_init step6.\n");
+        printk(BIOS_INFO, "rs690_gfx_init step6.\n");
 
 	/* step 7 compliance state, (only need if CMOS option is enabled) */
 	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
@@ -518,64 +518,64 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 		/* release hold training for device 2. GFX initialization is done. */
 		set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
 		dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
-		printk_info("rs690_gfx_init step7.\n");
+		printk(BIOS_INFO, "rs690_gfx_init step7.\n");
 		return;
 	}
 
 	/* step 8 common initialization */
 	/* step 8.1 sets RCB timeout to be 25ms */
 	set_pcie_enable_bits(dev, 0x70, 7 << 16, 3 << 16);
-	printk_info("rs690_gfx_init step8.1.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.1.\n");
 
 	/* step 8.2 disables slave ordering logic */
 	set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
-	printk_info("rs690_gfx_init step8.2.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.2.\n");
 
 	/* step 8.3 sets DMA payload size to 64 bytes */
 	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
-	printk_info("rs690_gfx_init step8.3.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.3.\n");
 
 	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
 	 * time out and go back to Detect Idle.*/
 	set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14);
-	printk_info("rs690_gfx_init step8.4.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.4.\n");
 
 	/* step 8.5 shortens the enumeration timer */
 	set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
-	printk_info("rs690_gfx_init step8.5.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.5.\n");
 
 	/* step 8.6 blocks DMA traffic during C3 state */
 	set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
-	printk_info("rs690_gfx_init step8.6.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.6.\n");
 
 	/* step 8.7 Do not gate the electrical idle form the PHY
 	 * step 8.8 Enables the escape from L1L23 */
 	set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30);
-	printk_info("rs690_gfx_init step8.8.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.8.\n");
 
 	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
 	 * SLOT_IMPLEMENTED@PCIE_CAP */
 	reg16 = pci_read_config16(dev, 0x5a);
 	reg16 |= 0x100;
 	pci_write_config16(dev, 0x5a, reg16);
-	printk_info("rs690_gfx_init step8.9.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.9.\n");
 
 	/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider.
 	 * This will workaround several failures reported by the PCI Compliance test under Vista DTM. */
 	set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 31, 0 << 31);
-	printk_info("rs690_gfx_init step8.10.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.10.\n");
 
 	/* step 8.11 Sets REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. */
 	set_pcie_enable_bits(nb_dev, 0x02, 1 << 0, 1 << 0);
-	printk_info("rs690_gfx_init step8.11.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.11.\n");
 
 	/* step 8.12 Sets REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */
 	set_pcie_enable_bits(nb_dev, 0x02, 1 << 6, 1 << 6);
-	printk_info("rs690_gfx_init step8.12.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.12.\n");
 
 	/* step 8.13 Sets CMGOOD_OVERRIDE. */
 	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
-	printk_info("rs690_gfx_init step8.13.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step8.13.\n");
 
 	/* step 9 Enable TLP Flushing, for non-AMD GFX devices and Hot-Plug devices only. */
 	/* skip */
@@ -619,7 +619,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 		dual_port_configuration(nb_dev, dev);
 		break;
 	default:
-		printk_info("Incorrect configuration of external gfx slot.\n");
+		printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n");
 		break;
 	}
 }
diff --git a/src/southbridge/amd/rs690/rs690_ht.c b/src/southbridge/amd/rs690/rs690_ht.c
index ef4b34296e..26824b5322 100644
--- a/src/southbridge/amd/rs690/rs690_ht.c
+++ b/src/southbridge/amd/rs690/rs690_ht.c
@@ -53,7 +53,7 @@ static void pcie_init(struct device *dev)
 	/* Enable pci error detecting */
 	u32 dword;
 
-	printk_info("pcie_init in rs690_ht.c\n");
+	printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index 91e6bb1066..ad2e871db4 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -110,7 +110,7 @@ static void pcie_init(struct device *dev)
 	/* Enable pci error detecting */
 	u32 dword;
 
-	printk_debug("pcie_init in rs690_pcie.c\n");
+	printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n");
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
@@ -168,7 +168,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
 *****************************************************************/
 void enable_pcie_bar3(device_t nb_dev)
 {
-	printk_debug("enable_pcie_bar3()\n");
+	printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
 	set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
 
@@ -184,7 +184,7 @@ void enable_pcie_bar3(device_t nb_dev)
 *****************************************************************/
 void disable_pcie_bar3(device_t nb_dev)
 {
-	printk_debug("disable_pcie_bar3()\n");
+	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
 	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
 	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
@@ -206,7 +206,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	device_t sb_dev;
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
-	printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
+	printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
 
 	/* init GPP core */
 	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,
@@ -262,7 +262,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 			PcieReleasePortTraining(nb_dev, dev, port);
 			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
 				u8 res = PcieTrainPort(nb_dev, dev, port);
-				printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res);
+				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
 				if (res) {
 					AtiPcieCfg.PortDetect |= 1 << port;
 				}