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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-06-28 15:36:57 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-10-29 00:19:12 +0100
commitcab9efb2be41ffbc2e6d97b2994915d8de2ccd84 (patch)
tree6fbd329169cadc826aa7bd944885856cc00fa598 /src/southbridge/amd/rs690
parent38b98546a7ae1b795d8f2c1b9647af77e508edd4 (diff)
downloadcoreboot-cab9efb2be41ffbc2e6d97b2994915d8de2ccd84.tar.xz
southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/6147 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/rs690')
-rw-r--r--src/southbridge/amd/rs690/cmn.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c
index 05a47b3870..86a6976606 100644
--- a/src/southbridge/amd/rs690/cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
@@ -285,10 +285,11 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
/* set bit8=1, bit0-2=bit4-6 */
u32 tmp;
reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
- tmp = (reg >> 4) && 0x3; /* get bit4-6 */
+ tmp = (reg >> 4) & 0x07; /* get bit4-6 */
reg &= 0xfff8; /* clear bit0-2 */
reg += tmp; /* merge */
reg |= 1 << 8;
+ nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
count++; /* CIM said "keep in loop"? */
} else {
res = 1;